NMS Accelerator Circuitry for Parallel Object Detection
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Solution Overview
Problem
Current Non-Maximum Suppression (NMS) algorithms, such as GreedyNMS, are a performance bottleneck in convolutional object detection pipelines due to their sequential nature, which cannot be parallelized, leading to inefficiencies in inference time despite advancements in hardware and convolutional operations.
Innovation Solution
The proposed accelerator circuitry employs sets of processing elements communicatively coupled to data buffers, performing parallel computations to project bounding boxes onto confidence score maps, partitioning, and storing score map cells at kernel indices, enabling efficient object detection by bypassing arbitration modules and optimizing score map processing across multiple stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If GreedyNMS algorithm is used for object detection, then detection accuracy is maintained, but inference time increases significantly due to sequential processing
Solution Approach 1:
The patent segments the NMS process into multiple independent stages: confidence score calculation, bounding box filtering, and suppression decision-making. Each stage processes data independently and can be executed in parallel, eliminating the sequential dependency of GreedyNMS while maintaining detection accuracy through systematic multi-stage filtering
Solution Approach 2:
The patent transforms the traditional 2D bounding box problem into a 3D confidence score map by adding the confidence dimension. This allows parallel processing across multiple score thresholds simultaneously, converting the sequential 1D NMS operation into a parallel 3D operation that maintains accuracy while reducing inference time
2Productivity
If hardware accelerators are added to speed up NMS, then processing speed increases, but device complexity increases
Solution Approach 1:
The patent designs a unified NMS accelerator architecture that handles multiple NMS variants (standard NMS, soft-NMS, angle NMS) and different object detection models through a single configurable hardware platform. This multi-functional design achieves high processing speed without proportionally increasing complexity, as the same hardware resources are reused across different operations
Solution Approach 2:
The patent implements dynamically configurable hardware parameters including adjustable confidence thresholds, flexible bounding box overlap criteria, and adaptive suppression rates. This dynamic configurability allows the hardware accelerator to adapt to different detection scenarios without requiring multiple dedicated hardware units, thereby maintaining processing speed while controlling complexity
Data Source
AI summary
This document describes an accelerator circuitry for facilitating acceleration of non-maximum suppression (NMS) for detection of objections within an image.