Artificial Neural Network Circuit with Threshold Memory Cells
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Solution Overview
Problem
Existing artificial neural network circuits face high power consumption and area requirements due to the use of digital-to-analog converters for batch normalization in binary neural networks, particularly in resistive memory-based systems.
Innovation Solution
An artificial neural network circuit design that includes unit weight memory cells and threshold memory cells connected through pass transistors, with a sense amplifier for comparing output signals, eliminating the need for digital-to-analog converters and allowing for reduced power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital-to-analog converter (DAC) is used to generate threshold for batch normalization, then the neural network can perform batch normalization, but the area and power consumption increase significantly
Solution Approach 1:
The patent extracts the threshold generation function from the traditional DAC-based approach and implements it directly within the resistive memory array using dedicated threshold memory cells. This removes the need for external DAC circuitry, significantly reducing area while maintaining batch normalization capability
Solution Approach 2:
The patent introduces threshold memory cells as intermediary elements between the input neurons and the sense amplifiers. These threshold cells store threshold values and enable comparison operations without requiring DAC conversion, thus eliminating the area overhead of DAC circuits
2Reliability
If a digital-to-analog converter (DAC) is used to generate threshold for batch normalization, then the neural network can perform batch normalization, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming DAC circuitry from the system by integrating threshold storage and comparison functions directly into the resistive memory array, thereby eliminating the primary source of excess power consumption
Solution Approach 2:
The resistive memory array performs self-service by using its inherent resistance properties to store threshold values and perform comparison operations. This eliminates the need for external power-intensive conversion circuits and leverages the natural characteristics of the memory devices
3Adaptability or versatility
If the sense amplifier is designed to handle the whole threshold range, then it can accommodate varying thresholds, but the required area increases
Solution Approach 1:
The patent segments the threshold range into discrete levels stored in individual threshold memory cells. Each cell stores a specific threshold value, allowing the sense amplifier to compare against predefined thresholds rather than handling the entire continuous range, thus reducing amplifier area
Solution Approach 2:
The patent uses partial action by implementing threshold comparison at the memory cell level rather than requiring the sense amplifier to handle the full dynamic range. Each threshold cell provides a localized comparison function, reducing the burden on the sense amplifier
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces overall power consumption and area requirements by eliminating the need for digital-to-analog converters and enabling the use of sense amplifiers with smaller dynamic ranges, enhancing the efficiency of batch normalization in binary neural networks.
Implementation Method 1
A resistive memory is a non-volatile memory which represents weight information with the resistance (or conductivity) of the corresponding device
Implementation Method 2
a sense amplifier configured to compare output signals of neurons output by the weight column with threshold signals output by the threshold column and output comparison results
Data Source
AI summary
Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.