Neural Network Instruction Streaming for Hardware Efficiency

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Solution Overview

Problem

Implementing artificial neural networks on hardware platforms is challenging due to the substantial research and resource requirements, as existing solutions do not efficiently utilize hardware resources for neural network execution.

Innovation Solution

The approach involves deconstructing artificial neural networks into an instruction stream format comprising opcodes, addresses, and data, which can be executed by a computer processor, allowing for parallel execution of neural network operations and efficient use of hardware resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If artificial neural networks are implemented on hardware platforms using existing solutions, then the network can perform inference and training operations, but the hardware resources are not efficiently utilized and substantial research effort is required

Engineering Contradiction:
Improveneural network execution efficiencyVSAvoidhardware research requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a software-based instruction stream that copies the functionality of neural network operations into a format executable by general-purpose processors. Instead of designing specialized hardware, the invention translates neural network operations into instruction streams with opcodes, addresses, and data that can be executed on existing hardware platforms, eliminating the need for substantial hardware research while maintaining execution efficiency

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The instruction stream format designed in the patent is universally applicable to different neural network architectures and operations. The same instruction stream mechanism can handle various layer types, activation functions, and network configurations, allowing a single hardware platform to efficiently execute diverse neural network workloads without requiring architecture-specific hardware design

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If neural networks are deconstructed into instruction stream format for processor execution, then hardware resource utilization improves and parallel execution is enabled, but the implementation complexity of the instruction stream format increases

Engineering Contradiction:
Improvehardware resource utilizationVSAvoidinstruction stream format complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments neural network operations into discrete instruction stream components including opcodes that specify operations, addresses that specify data locations, and data fields that contain actual values. This segmentation allows the complex neural network computation to be broken down into manageable, executable instructions that can be processed efficiently by general-purpose processors while maintaining clear structure and organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the traditional hardware-oriented neural network implementation into a software instruction dimension. By representing neural network operations as sequential instructions with temporal ordering rather than spatial hardware configurations, the invention enables execution on standard processors while exploiting parallelism through instruction-level and data-level parallelism in the software domain

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of time

If instruction streams are used to implement neural networks, then parallel execution of operations is achieved reducing execution time, but the processing overhead for instruction interpretation increases

Engineering Contradiction:
Improveneural network execution timeVSAvoidprocessor energy consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent designs the instruction stream format to enable continuous execution of neural network operations without interruption for format conversion or interpretation. The instruction stream maintains a consistent structure with opcodes, addresses, and data that can be processed continuously by the processor, minimizing overhead and maximizing utilization of processing resources throughout the entire neural network computation

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentEP4052188B1Neural network instruction streaming
Publication Date: 2024.07.31 RAYTHEON CO
  • EP4052188B1 patent drawingFigure 1
  • EP4052188B1 patent drawingFigure 2~3
  • EP4052188B1 patent drawingFigure 4

AI summary

An artificial neural network is implemented via an instruction stream. A header of the instruction stream and a format for instructions in the instruction stream are defined. The format includes an opcode, an address, and data. The instruction stream is created using the header, the opcode, the address, and the data. The artificial neural network is implemented by providing the instruction stream to a computer processor for execution of the instruction stream.