Hardware Acceleration Circuit for Neural Network Non-Linear Functions

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Solution Overview

Problem

Existing technologies face inefficiencies and increased system bandwidth and power consumption when calculating non-linear function values, particularly in artificial neural networks, due to overheads from job migration between hardware circuits and general-purpose CPUs/GPUs.

Innovation Solution

A hardware acceleration circuit is designed to reduce the calculation amount for data processing by including an exponential function module, an adder, and processing circuits that convert and process exponential function values to obtain a specific function value more efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If non-linear function values are calculated using general-purpose CPUs or GPUs, then calculation flexibility is maintained, but job migration overhead increases and processing efficiency decreases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidjob migration overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the non-linear function calculation capability from general-purpose CPUs/GPUs and implements it as a dedicated hardware module within the neural network processing unit. This separation allows the NNPU to handle non-linear functions internally without job migration to external processors, eliminating migration overhead while maintaining calculation flexibility through configurable hardware modules.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a dedicated non-linear function calculation module as an intermediary component between the neural network data processing pipeline and the output. This intermediary module specialized for non-linear operations (softmax, sigmoid, etc.) enables efficient in-house calculation within the NNPU, avoiding the need to migrate jobs to external CPUs or GPUs.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If non-linear function values are calculated using hardware circuits, then processing speed increases, but system bandwidth consumption increases

Engineering Contradiction:
Improvecalculation speedVSAvoidsystem bandwidth
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent merges the non-linear function calculation operations with the existing neural network data processing flow within the same hardware pipeline. By integrating softmax, sigmoid, and other non-linear function modules directly into the NNPU's data processing path, the system eliminates intermediate data transfers to external memory or processors, thereby reducing bandwidth consumption while maintaining high calculation speed.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If non-linear function values are calculated using hardware circuits, then processing speed increases, but power consumption increases

Engineering Contradiction:
Improvecalculation speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by stationary object

Solution Approach 1:

The patent implements local quality by designing specialized hardware modules for specific non-linear functions (softmax, sigmoid, etc.) that are activated only when needed. Each function module is optimized for its specific operation, allowing the NNPU to consume power only for the actual calculations being performed rather than maintaining continuous high-power operation. This localized, on-demand activation reduces overall power consumption while maintaining high calculation speed when non-linear functions are required.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250156151A1Hardware acceleration circuit, data processing acceleration method, chip, and accelerator
Publication Date: 2025.05.15 GUANGZHOU XIAOPENG MOTORS TECH CO LTD
  • US20250156151A1 patent drawing
  • US20250156151A1 patent drawing
  • US20250156151A1 patent drawing

AI summary

A hardware acceleration circuit, a data processing acceleration method, a chip, and an accelerator are provided. The hardware acceleration circuit includes: an exponential function module, configured to obtain exponential function values of a plurality of data elements in a data set; an adder, configured to obtain an addition operation result of the exponential function values; a first processing circuit, configured to perform preset processing on the addition operation result, to process the addition operation result into at least first data and second data; a second processing circuit, configured to perform preset processing on at least the first data and the second data, to obtain a reciprocal of the addition operation result; and a third processing circuit, configured to perform preset processing on an exponential function value of an ith data element in the data elements and the reciprocal, to obtain a specific function value of the ith data element.