Neural Network Unit Interrupts Core via Status Condition Register

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Solution Overview

Problem

Current neural network processing technologies face inefficiencies in performing computations associated with artificial neural networks, particularly in handling large numbers of connections and weights, leading to suboptimal performance and resource utilization.

Innovation Solution

A programmable apparatus with a neural network unit (NNU) that includes a status register and condition register, allowing for interrupt requests to be generated based on specific conditions, enabling efficient processing and resource management by dynamically configuring neural processing units (NPUs) to perform operations on multiple data sizes and selectively write back results, thereby optimizing neural network computations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If neural network units continuously monitor and manage processing conditions, then processing efficiency and resource utilization improve, but device complexity and overhead increase

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The neural network unit autonomously monitors its own processing conditions and generates interrupt requests without external intervention. The status register automatically tracks processing state, and the control logic self-evaluates conditions to determine when interrupts are necessary, enabling the system to manage itself and reduce overall system complexity despite the added monitoring functionality.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements a feedback mechanism where the status register continuously monitors processing conditions and feeds this information back to the control logic. When specified conditions are met, the control logic generates interrupt requests to the processing core, creating a closed-loop system that adapts to processing needs and optimizes resource utilization dynamically.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If the neural network unit implements comprehensive condition monitoring and interrupt generation capabilities, then resource management and processing optimization improve, but the number of registers and control logic complexity increase

Engineering Contradiction:
Improveresource management capabilityVSAvoidcontrol logic complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The control logic is segmented into distinct functional components: a status register that automatically tracks processing conditions, a condition evaluation unit that compares status against thresholds, and an interrupt generation unit that signals the processing core. This segmentation reduces overall complexity by distributing functions across specialized modules rather than requiring a monolithic complex controller.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The status register serves multiple functions: it tracks processing completion status, monitors resource utilization levels, and evaluates conditions for interrupt generation. By making the status register multi-functional, the system reduces the need for separate dedicated circuits for each monitoring function, thereby reducing overall device complexity while maintaining comprehensive resource management capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11221872B2Neural network unit that interrupts processing core upon condition
Publication Date: 2022.01.11 VIA ALLIANCE SEMICON CO LTD
  • US11221872B2 patent drawing
  • US11221872B2 patent drawing
  • US11221872B2 patent drawing

AI summary

A programmable apparatus includes a program memory that holds instructions of a program fetched and executed by the apparatus, a data memory that holds data processed by the instructions, a status register that holds a status having fields: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count that indicates a number of times an operation specified in a current program instruction remains to be performed. A condition register has condition fields corresponding to the status register fields. Control logic generates an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.