No-Code Clock Element Design for Automated RTL Generation
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Solution Overview
Problem
The existing system-on-chip (SoC) design process is inefficient due to repeated work across stages, requiring manual coding and rework when design changes occur, leading to significant time and labor costs.
Innovation Solution
A clock element no-code design system that automatically generates register transfer level (RTL) code for clock management units, allowing users to design clock elements without coding knowledge, by setting field values and generating hardware code through a graphical user interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual Verilog coding is used for clock element design, then design flexibility is maintained, but time and labor costs increase significantly
Solution Approach 1:
The system enables self-service automation where the clock element design process automatically generates RTL code from graphical clock diagrams. The design tool itself performs the coding task that would otherwise require manual effort, eliminating the need for developers to write Verilog code manually while maintaining design flexibility through the graphical interface.
2Adaptability or versatility
If design changes are made during the project, then adaptability is improved, but repeated work and rework are required
Solution Approach 1:
The system performs preliminary action by automatically generating RTL code from the graphical clock diagram at the point of design. When design changes occur, users simply modify the graphical diagram and the system automatically regenerates the code, eliminating the need for manual re-coding and reducing repeated work significantly.
3Productivity
If automatic RTL code generation is implemented, then productivity is improved, but coding knowledge is required
Solution Approach 1:
The system introduces an intermediary graphical clock diagram as a mediator between the user's design intent and the RTL code generation. Users interact with the visual diagram interface which automatically translates into RTL code, eliminating the need for users to directly write or understand Verilog code while maintaining automatic code generation capabilities.
Data Source
AI summary
Disclosed are a clock element no-code design system including: a memory configured to store at least one instruction; a clock component storage configured to store clock component information defining an address and field values of a register of a clock instance generated based on a clock component; a hardware code logic storage configured to store a hardware code logic for generating hardware code based on a designed clock instance; and at least one processor configured to execute the at least one instruction stored in the memory, wherein the at least one instruction includes instructions to: design a new clock instance by setting field values of a register defining a function of the new clock instance based on previously generated clock instance information and the clock component information, and generate hardware code by generating a clock module and a register module corresponding to the clock module based on the field values of the register of the designed new clock instance and the hardware code logic, and combining the clock module and the register module.