No-Code Clock Management Unit Design for SoC Hardware Generation
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Solution Overview
Problem
The existing SoC design process is inefficient due to repeated work across stages, labor-intensive manual coding, and the need for stakeholders to adapt to changing requirements, leading to significant time and resource costs.
Innovation Solution
A no-code approach for designing clock management units within SoCs, utilizing a system that includes a memory, clock component storage, and hardware code logic storage to automatically generate hardware code for clock elements and their connections, considering the settings required throughout the clock design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual Verilog coding is used for clock management unit design, then design flexibility and customization are improved, but design time and labor costs increase significantly
Solution Approach 1:
The system performs preliminary actions by pre-defining clock element templates with standard functions and configurations. These templates are prepared in advance and can be directly instantiated during design, eliminating the need to write Verilog code from scratch for common clock management components.
Solution Approach 2:
The system uses copying by allowing designers to replicate existing clock element configurations and instantiate them multiple times with different parameters. This enables rapid deployment of standardized clock management units across different design contexts without repetitive manual coding.
2Ease of manufacture
If multiple design stages with independent stakeholder work are used, then specialized expertise for each stage is improved, but repetitive tasks and time costs increase
Solution Approach 1:
The system merges multiple design stages into a unified automated flow. The generation of power and clock diagrams, Verilog code, UPF files, and SDC files is integrated into a single coordinated process, eliminating the need for separate manual stages and reducing repetitive tasks.
Solution Approach 2:
The system implements feedback mechanisms where design parameters specified at higher levels automatically propagate through subsequent design stages. This ensures consistency across different design artifacts and reduces the need for manual adjustments and iterations between stages.
3Reliability
If initial design work is repeated to resolve simulation issues, then design accuracy is improved, but time and labor costs increase
Solution Approach 1:
The system performs preliminary verification by generating complete design artifacts including testbenches and constraint files in the initial automated flow. This allows simulation and verification to be performed early without requiring repeated design iterations, as all necessary design elements are already properly configured.
Data Source
AI summary
Disclosed are clock management unit design system and method for designing an internal function module of clock elements constituting a clock management unit and connections between the clock elements using a no-code approach. A clock management unit design system using a no-code approach includes: a memory configured to store at least one instruction; a clock component storage configured to store clock component information constituting a clock management unit; a hardware code logic storage configured to store hardware code logic for generating a designed clock management unit as hardware code; and at least one processor configured to execute the at least one instruction stored in the memory