No-Code Programmable Sequencer for Flexible SoC Power Sequences
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Solution Overview
Problem
Conventional power controllers in system-on-chip (SoC) designs are inflexible and costly due to their fixed sequencer nature, leading to inefficiencies and increased costs when dealing with complex power up/down sequences, and require manual coding and repeated design efforts across multiple stages, consuming significant time and resources.
Innovation Solution
A no-code programmable sequencer design system that automatically generates register transfer level (RTL) code for power management units, allowing flexible power up/down sequences without manual coding, by using a memory, component storage, and processor to generate power instances and instruction instances based on power components and instruction components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed sequencer using state machine is used for power control, then the design is simple and execution is fast, but the flexibility to change power up/down sequences is limited
Solution Approach 1:
The patent applies dynamics by replacing the fixed state machine with a programmable sequencer that can dynamically change its behavior through configuration data. The sequencer reads power up/down sequences from memory or registers, allowing the sequence to be modified without changing the hardware design. This enables the system to adapt to different power management requirements while maintaining a consistent architectural structure.
2Adaptability or versatility
If commercial microcontroller units are used for power control, then programmable sequences are achieved, but system cost increases significantly
Solution Approach 1:
The patent implements universality by designing a programmable sequencer that can serve multiple power domains within an SoC using a single unified architecture. Instead of deploying separate commercial MCUs for each power domain, the same programmable sequencer structure is reused across different domains, configured through software or configuration data. This multi-functional approach achieves the programmability of MCUs while reducing hardware cost and complexity.
Solution Approach 2:
The patent replaces expensive commercial microcontroller units with a cost-effective programmable sequencer implementation using standard logic elements and memory. The solution uses readily available, lower-cost components to achieve the required functionality, sacrificing the full programmability of MCUs but retaining essential power sequencing capabilities at a fraction of the cost.
3Manufacturing precision
If manual Verilog coding is performed for each design stage, then detailed control is achieved, but time and resource consumption increase significantly
Solution Approach 1:
The patent applies self-service by enabling the programmable sequencer to be configured and programmed automatically through software tools and configuration data rather than requiring manual Verilog coding for each design modification. The configuration data can be generated automatically from power management requirements, and the sequencer loads and executes these configurations without human intervention in the coding process. This maintains design precision while dramatically improving productivity by eliminating repetitive manual coding tasks.
Data Source
AI summary
A system and method for designing a programmable sequencer capable of modifying power up and power down sequences for power control in a power domain using a no-code approach. According to one embodiment, the system includes a memory to store at least one instruction, a component storage configured to store power component information and instruction component information, a code logic storage configured to store software code logic for generating executable code based on an instruction instance, and at least one processor configured to execute the stored instruction(s). The instruction(s) include operations for generating at least one power instance based on a power component, generating a first instruction instance based on an instruction component, determining a target power instance among the generated power instances and setting a value, and generating code including an instruction, a register address, and data based on the instruction instance, the target power instance, and the value.