No-Mold Shelf Package Layout for Better Thermal Compression Bonding
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Solution Overview
Problem
Existing semiconductor packaging processes with mold shelf designs face challenges in thermal conductivity, leading to reduced process windows and higher yield losses during thermal compression bonding due to the low-thermal conductivity of mold materials.
Innovation Solution
The implementation of semiconductor packages with dummy silicon regions/edges that replace mold shelves, enhancing thermal conductivity and allowing for improved heat transfer during thermal compression bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If mold shelf package design is used in existing semiconductor packaging processes, then the packaging structure is simple and manufacturing is easier, but the thermal conductivity is low leading to reduced process windows and higher yield losses during thermal compression bonding
Solution Approach 1:
The patent removes the mold shelf structure from the package design. By extracting this low-thermal-conductivity component, the patent enables direct thermal contact between the substrate and the bonding interface, thereby improving thermal conductivity and process window without complicating the manufacturing process
Solution Approach 2:
The patent employs composite material strategies by combining different substrate materials with varying thermal properties. The substrate is designed with regions of high thermal conductivity to facilitate heat transfer during bonding, while maintaining structural integrity and manufacturing simplicity
2Temperature
If high-thermal conductivity mold materials are used to improve heat transfer, then thermal conductivity increases, but reliability issues increase due to higher issues with such mold materials and filler materials conductivity
Solution Approach 1:
The patent eliminates the mold material entirely by removing the mold shelf structure. This extraction approach avoids all reliability issues associated with mold materials and filler materials, while still achieving high thermal conductivity through direct substrate-to-bonding interface contact
Solution Approach 2:
The patent changes the thermal conductivity parameter of the packaging structure by transitioning from mold material to substrate material. The substrate's inherent high thermal conductivity replaces the need for specialized high-conductivity mold materials, improving both thermal performance and reliability
3Power
If bond head peak temperature and pedestal temperature are increased to improve bonding, then thermal conductivity effect is enhanced, but substrate expansion increases and solder melting becomes non-uniform leading to higher process time
Solution Approach 1:
The patent applies local quality by creating regions of high thermal conductivity at the bonding interface while maintaining moderate temperatures elsewhere. The removed mold shelf allows concentrated heat delivery exactly where needed, achieving uniform solder melting without excessive substrate expansion or increased process time
4Temperature
If TCB pedestal temperature is increased to improve bonding, then heat transfer is enhanced, but the process window decreases due to flux activity limitations and site time constraints
Solution Approach 1:
The patent changes the thermal conductivity parameter of the packaging structure to achieve better heat transfer at lower temperatures. By removing the mold shelf, the system achieves effective bonding with reduced pedestal temperature, thereby expanding the process window and maintaining productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution increases the thermal conductivity of advanced packaging technologies, expands the process window, and enhances yield while maintaining cost-effectiveness.
Implementation Method 1
The implementation of semiconductor packages with dummy silicon regions/edges that replace mold shelves, enhancing thermal conductivity and allowing for improved heat transfer during thermal compression bonding
Data Source
AI summary
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.