Noble Metal Catalyst Etching for DRAM Storage Node Holes
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) devices require periodic refresh operations due to capacitors slowly discharging, leading to data loss, and there is a need for capacitors with high capacitance values in highly integrated circuit devices.
Innovation Solution
A method of fabricating semiconductor devices involves forming an interlayer dielectric layer, a storage node contact, and a mold layer with a noble metal pattern as a catalyst for etching, using etchants like H2O2/HF, HCl, or H2SO4, to create storage node holes with equivalent upper and lower widths, enabling the formation of capacitors with high capacitance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form storage node holes, then the manufacturing process is simpler, but the upper and lower portions of the storage node hole have different widths, reducing capacitance efficiency
Solution Approach 1:
A mold layer is introduced as an intermediary component between the storage node contact and the first electrode. This mold layer enables precise control of the storage node hole geometry, ensuring uniform upper and lower widths while maintaining etch selectivity through its distinct material properties.
Solution Approach 2:
The etching process parameters are changed by introducing a catalyst pattern that modifies the chemical etching behavior. The catalyst pattern enables selective etching of the mold layer while preserving the uniform geometry of the storage node hole, achieving both precision and processability.
2Quantity of substance
If capacitor aspect ratio is increased to improve capacitance, then capacitance value increases, but leakage current may increase and manufacturing becomes more difficult
Solution Approach 1:
Different materials with specific local properties are used at different locations: the mold layer provides structural definition, the catalyst pattern enables selective etching, and the etch stop layer prevents over-etching. This local optimization ensures uniform hole geometry that maintains high capacitance while controlling leakage.
Solution Approach 2:
The mold layer and catalyst pattern are formed in advance before the actual etching of the storage node hole. This preliminary structuring ensures that the etching process proceeds uniformly from top to bottom, preventing geometry variations that could lead to increased leakage current.
3Manufacturing precision
If etching selectivity is improved to protect surrounding structures, then manufacturing precision increases, but additional process steps are required
Solution Approach 1:
The mold layer serves multiple functions simultaneously: it defines the storage node hole geometry, provides etch selectivity through its material composition, and acts as a structural template. This multi-functionality achieves high etching precision without requiring separate dedicated structures for each function.
Solution Approach 2:
The etching system uses composite material layers with distinct chemical properties: the mold layer (polysilicon or silicon oxide), etch stop layer (silicon nitride), and catalyst pattern (noble metal). These composite materials provide inherent etch selectivity that protects surrounding structures while enabling precise hole formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in semiconductor devices with capacitors having a high aspect ratio and uniform width, increasing capacitance while reducing leakage current, thus addressing the need for efficient data storage in DRAM devices.
Implementation Method 1
Etching the mold layer may include etching the mold layer using a noble metal pattern as a catalyst
Implementation Method 2
performing a wet etching process using an etchant including H2O2/HF, HCl, H3PO4 or H2SO4
Data Source
AI summary
Fabricating methods of a semiconductor device are provided. The fabricating methods may include forming a mold layer, forming a catalyst pattern including noble metal on the mold layer and etching the mold layer using the catalyst pattern as a catalyst. Etching the mold layer may include performing a wet etching process.