Noble Metal Catalyst Etching for Semiconductor Substrates

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Solution Overview

Problem

Existing etching methods for semiconductor substrates often result in the formation of porous residual portions and uneven etching patterns, particularly when using metal-assisted chemical etching (MacEtch), which can hinder the production of high-quality semiconductor chips.

Innovation Solution

The method involves forming an uneven structure with a projection on the semiconductor substrate, depositing a noble metal catalyst layer on the projection, and using an etchant to etch the substrate, preventing the catalyst from diffusing under the mask layer and thus avoiding the formation of porous residues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If metal-assisted chemical etching (MacEtch) is used to etch semiconductor substrates, then etching efficiency is improved, but porous residual portions are formed and etching uniformity deteriorates

Engineering Contradiction:
Improveetching efficiencyVSAvoidetching uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by forming projections with specific geometric features (rounded corners, specific aspect ratios) in strategic locations on the substrate. These localized structural modifications create controlled etching behavior at specific regions while maintaining overall etching uniformity, resolving the contradiction between efficient etching and uniformity by making the substrate surface non-uniform in a controlled manner.

Inventive Principle:
Principle #3Local quality

2Productivity

If catalyst layer is deposited on flat substrate surface, then catalytic etching is achieved, but catalyst diffuses under mask layer causing unwanted etching

Engineering Contradiction:
Improvecatalytic etchingVSAvoidetching pattern control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by pre-forming projections on the substrate surface before depositing the catalyst layer. These projections serve as predetermined sites that confine the catalyst to specific locations, preventing lateral diffusion under the mask layer. The projections are formed in advance with geometric features that actively prevent catalyst migration, ensuring precise etching pattern control while maintaining catalytic etching efficiency.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If conventional etching methods are used, then process simplicity is maintained, but porous residues are generated reducing chip quality

Engineering Contradiction:
Improveprocess simplicityVSAvoidresidue formation
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the geometric parameters of the substrate surface - specifically creating projections with controlled dimensions, aspect ratios, and corner radii. These parameter modifications to the substrate topology enable the etching process to proceed without generating porous residues, while adding only a single projection formation step to the conventional process flow.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents the generation of porous residual portions, allowing for controlled and directional etching that enhances the quality and yield of semiconductor chips by ensuring uniform etching without cross-directional etching issues.

Implementation Method 1

forming a catalyst layer including a noble metal on the projection; and supplying an etchant to the catalyst layer to etch the semiconductor substrate with an assist from the noble metal as a catalyst

Methodology Applied
Scientific EffectCatalysis: Catalysis

Data Source

PatentUS10854466B2Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
Publication Date: 2020.12.01 KK TOSHIBA
  • US10854466B2 patent drawing
  • US10854466B2 patent drawing
  • US10854466B2 patent drawing

AI summary

An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.