NoC Buffer Sizing via Machine Learning Optimization

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Solution Overview

Problem

Current methods for sizing flow control buffers in Network on Chip (NoC) communication infrastructure face challenges due to increasing complexity and the need for varying buffer sizes across channels, which is costly in terms of power, area, and performance, especially in high-performance systems where low latency and high bandwidth are critical.

Innovation Solution

The use of incremental dynamic optimization and machine learning to determine arrival and departure characteristics of buffers, optimizing buffer depth based on these characteristics, and iteratively refining buffer sizes through simulations to achieve optimal performance metrics such as bandwidth and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If varying buffer sizes are used across channels to optimize performance, then communication efficiency is improved, but power consumption and area requirements increase

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting buffer sizes based on traffic conditions and channel characteristics. The buffer depth is optimized as a variable parameter rather than a fixed value, allowing the system to adapt to different communication scenarios and achieve high communication efficiency while avoiding the constant power consumption and area overhead of uniformly large buffers.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If larger buffer sizes are used to handle traffic variability, then reliability is improved, but device complexity and area increase

Engineering Contradiction:
Improvetraffic handling reliabilityVSAvoidbuffer configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamics by making buffer sizes adaptive rather than static. The buffer configuration changes dynamically based on observed traffic patterns, channel utilization, and performance metrics. This allows the system to maintain high reliability for handling traffic variability while reducing the need for overly complex fixed buffer configurations that would be required to accommodate all possible traffic scenarios simultaneously.

Inventive Principle:
Principle #15Dynamics

3Productivity

If machine learning based optimization is applied to determine buffer characteristics, then performance optimization is improved, but computational complexity increases

Engineering Contradiction:
Improveperformance optimizationVSAvoidcomputational complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-training machine learning models offline to determine optimal buffer characteristics for different traffic scenarios. The trained models are then deployed to make rapid predictions during runtime without requiring complex real-time computations. This approach achieves high performance optimization while keeping the runtime computational complexity manageable by shifting the heavy computational burden to the offline training phase.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10523599B2Buffer sizing of a NoC through machine learning
Publication Date: 2019.12.31 INTEL CORP
  • US10523599B2 patent drawing
  • US10523599B2 patent drawing
  • US10523599B2 patent drawing

AI summary

The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.