On-Chip Network Buffering Architecture for Packet Injection
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Solution Overview
Problem
Current on-chip communication architectures face high latency and memory inefficiency due to the need for separate channels and fixed flit sizes, leading to increased memory access and storage requirements for header and payload data conversion between network-on-chip and on-chip bus systems.
Innovation Solution
The method involves storing control data and actual data in separate memory means, allowing simultaneous writing and reading, and using flags to indicate payload presence, enabling efficient data packet elaboration and transfer between electronic devices through network-on-chip and on-chip bus systems, with separate FIFOs for headers and payloads to manage varying packet sizes and formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If header and payload are stored in successive address columns in memory to avoid mixing, then data integrity is maintained, but latency increases and memory access time is extended
Solution Approach 1:
The patent segments the memory structure into separate storage regions for header data and payload data, allowing them to be accessed independently through separate address columns. This segmentation enables parallel access operations, reducing the latency penalty associated with maintaining data integrity while preventing header-payload mixing.
2Quantity of substance
If memory word size is increased to accommodate maximum data bus size and flit size, then storage capacity is improved, but memory resource waste increases when packets have smaller sizes
Solution Approach 1:
The patent applies local quality by allowing different portions of the memory structure to have different effective sizes based on the actual packet being stored. The header and payload can be stored in optimally-sized regions within the memory word, rather than requiring the entire memory word to accommodate the maximum possible packet size. This reduces memory waste while maintaining sufficient storage capacity.
3Reliability
If separate channels are used for control data and actual data transmission on on-chip buses, then communication reliability is improved, but device complexity and memory requirements increase
Solution Approach 1:
The patent merges the storage of header and payload data into a unified memory structure with separate addressable regions, rather than requiring completely separate memory systems for control and data channels. This merging approach maintains the reliability benefits of separate channel processing while reducing the overall memory requirements and device complexity compared to fully separate storage systems.
Data Source
AI summary
This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising:retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred;storing said request control and data to be transferred in memory means provided in an network interface (NI); andelaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively;The control data and the actual data to be transferred are stored in separate first and second memory means.