Network-on-Chip Cache Controller Integration for Faster Memory Access
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Solution Overview
Problem
Integrated circuit devices with programmable logic circuitry face performance bottlenecks due to external memory access times, and implementing cache memories increases design, programming, and power costs, especially when cache controller circuitry is external or in another IC device.
Innovation Solution
Integrate cache controller circuitry within the Network-on-Chip (NoC) to reduce complexity and cost, and enhance performance by reducing inter-chip connections and routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If cache memory is implemented for programmable logic, then access time to data is reduced, but design cost, programming cost, circuit area cost, and power cost increase
Solution Approach 1:
The cache controller circuitry is merged with the Network-on-Chip (NoC) infrastructure, combining two separate functions (cache control and network communication) into a single integrated unit. This reduces the overall device complexity by eliminating separate cache controller components while maintaining the performance benefits of cache memory.
Solution Approach 2:
The NoC infrastructure is enhanced to perform dual functions: traditional network communication and cache control operations. By making the NoC universal enough to handle both data transmission and cache management, the patent eliminates the need for dedicated cache controller circuitry, thereby reducing design and programming costs while improving memory access time.
2Loss of time
If cache memory is implemented for programmable logic, then access time to data is reduced, but circuit area cost and power cost increase
Solution Approach 1:
The cache controller functionality is merged into the existing NoC infrastructure, utilizing shared hardware resources such as routing networks, switches, and communication channels. This approach avoids duplicating circuit area for separate cache control components while still providing cache acceleration benefits.
Solution Approach 2:
The NoC components are designed to serve multiple purposes: network data transmission and cache memory management. By making the infrastructure universal, the patent eliminates the need for additional dedicated cache controller circuitry, thereby reducing overall circuit area occupation while maintaining fast memory access capability.
3Adaptability or versatility
If cache controller circuitry is external or in another IC device, then cache functionality is provided, but inter-chip communication bandwidth and access times increase
Solution Approach 1:
The cache controller functionality is extracted from external locations (separate IC devices or external controllers) and integrated directly into the NoC infrastructure within the same chip. This extraction eliminates the need for inter-chip communication for cache operations, thereby improving access speed while maintaining cache adaptability.
Solution Approach 2:
By merging the cache controller with the on-chip NoC infrastructure, the patent ensures that cache operations occur entirely within the chip boundaries, utilizing internal communication channels rather than external inter-chip connections. This integration maintains cache versatility while dramatically improving access speed by eliminating external communication bottlenecks.
Data Source
AI summary
An integrated circuit device includes logic circuitry and a Network-on-Chip (NoC). The logic circuitry performs one or more operations of an application. The NoC is coupled to the logic circuitry via a NoC master unit (NMU). The NoC includes cache controller circuitry that receives a first memory command from the logic circuitry via the NMU. Further, in response to data associated with the first memory command being stored within a cached memory, the cache controller circuitry executes the first memory command on the data of the cache memory.