NoC Processing Cluster Layout With Central Switch Data Exchange
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Solution Overview
Problem
Existing computer systems face challenges in efficiently managing data processing and communication between multiple processing elements, particularly in applications requiring massive signal processing and neural network implementations.
Innovation Solution
A data processing system with a control processor and multiple processing clusters organized in a Network on Chip (NoC) architecture, featuring a switch block for centralized data exchange, enabling efficient communication and data transfer between neighboring clusters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a mesh network is used to connect processing clusters, then data exchange between neighboring clusters is efficient, but the device complexity and routing management become difficult
Solution Approach 1:
A central switch block is introduced as an intermediary component to manage all data exchange between processing clusters. Instead of direct peer-to-peer connections in a mesh network, all communication routes through the central switch, which handles routing, switching, and arbitration functions. This simplifies the network topology while maintaining efficient data exchange capabilities.
2Device complexity
If a star-shaped Network on Chip is used with a central switch block, then the device complexity is reduced and routing is simplified, but the data transfer distance and potential bottlenecks increase
Solution Approach 1:
The network is segmented into multiple independent data channels, with each processing cluster having its own dedicated point-to-point channel to the central switch block. This segmentation allows parallel data transfers through different channels, preventing bottlenecks and maintaining high transfer speeds despite the star topology.
Solution Approach 2:
The central switch block dynamically configures connection paths and allocates bandwidth based on real-time communication demands. This dynamic resource allocation optimizes data transfer speed by prioritizing critical data flows and balancing the load across available channels, preventing the central switch from becoming a static bottleneck.
3Ease of operation
If multiple processing clusters are connected via a central hub, then ease of operation and centralized control are improved, but the loss of time for data access from peripheral nodes increases
Solution Approach 1:
The system implements preliminary action through buffer memory structures and prediction-based pre-fetching mechanisms. Frequently accessed data is pre-loaded into local buffers at processing clusters, and the central switch predicts future data needs based on access patterns, reducing actual data access time despite the centralized architecture.
Solution Approach 2:
The central switch block maintains continuous operation by implementing pipelined data processing and overlapping communication operations. While one data transfer is in progress, the switch prepares the next transfer, ensuring continuous useful action and minimizing idle time. This keeps the system efficiently utilizing available bandwidth and reduces average access time.
Data Source
AI summary
There is provided a data processing system comprising a control processor having access to memory, and a plurality of Processing Elements, PEs, organized in multiple processing clusters, each cluster comprising a multitude of said Processing Elements. The multiple processing clusters are arranged in a Network on Chip, NoC, connected, via a switch block, to the control processor, which is provided as a central hub, i.e. a root, for the Network on Chip, and the multiple processing clusters of Processing Elements being arranged at peripheral nodes, also being referred to as cluster nodes, of the Network on Chip. The Network on Chip is a network having multiple data channels connecting the switch block with the multiple processing clusters, with a point-to-point channel for each processing cluster. The multiple processing clusters are logically organized as an array with specific locations for the processing clusters in the array, and the switch block is configured for enabling exchange of data between processing clusters of neighboring locations in the array via the switch block.