Network-on-Chip Synthesis Using Clustering for Deadlock-Free Design
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Solution Overview
Problem
Designing a network-on-chip (NoC) that minimizes resource usage while avoiding cycles to prevent deadlocks, which is challenging due to physical constraints and the need for a connectivity map that honors these constraints without introducing new cycles.
Innovation Solution
The method involves clustering nodes and edges to transform the network into a deadlock-free and near-optimal structure, using edge and node clustering to reduce wiring and logic elements while maintaining physical constraints and avoiding cycle introduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the network is optimized to minimize resource usage, then the number of wires and logic elements is reduced, but the risk of introducing cycles that cause deadlocks increases
Solution Approach 1:
The patent applies preliminary action by performing cycle detection and prevention during the network synthesis and transformation process. The system analyzes the input network, identifies potential cycles, and proactively modifies the connectivity map before deployment to ensure deadlock-free operation while minimizing resources.
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring the network structure during transformation, detecting cycles, and adjusting the connectivity map accordingly. The system uses feedback from cycle detection algorithms to guide the optimization process, ensuring that resource minimization does not compromise deadlock-free operation.
2Quantity of substance
If the connectivity map is transformed to reduce wiring and switches, then resource usage is optimized, but the physical constraints of the floorplan may be violated
Solution Approach 1:
The patent applies local quality by performing localized transformations on the connectivity map that respect the physical floorplan constraints. The system identifies regions where transformations can be applied without violating manufacturing constraints, and applies optimizations locally rather than globally, preserving physical feasibility while reducing resources.
Solution Approach 2:
The patent uses parameter changes by adjusting the connectivity map parameters (such as routing paths and node connections) within the bounds of physical floorplan constraints. The system transforms the network by modifying connection parameters to reduce wiring and switches while ensuring that all transformations honor the physical layout requirements.
3Reliability
If the network synthesis process is made more complex to ensure deadlock-free operation, then reliability improves, but the runtime efficiency and productivity decrease
Solution Approach 1:
The patent applies partial action by implementing selective cycle detection and prevention only where necessary in the network synthesis process. Rather than performing exhaustive analysis on the entire network, the system focuses on critical paths and high-risk areas, achieving deadlock-free operation with reduced computational overhead and improved runtime efficiency.
Data Source
AI summary
System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC). The system applies a method of clustering to nodes and edges. The clustering transforms the network and produces a deadlock free and (near-)optimal network that honors the constraints of the input network's floorplan and specification.