Network on Chip Collapsible Queue Architecture
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Solution Overview
Problem
Traditional bus-based and crossbar interconnect architectures in computing systems do not scale well with increasing numbers of processing units, leading to delays in supplying instructions and data, and existing network on chip (NoC) architectures require efficient traffic management to maintain throughput.
Innovation Solution
Implementing a network on chip (NoC) architecture with centralized collapsible queues and control logic that selects non-contiguous queue entries for deallocation and shifts remaining entries to maintain full throughput, processing up to the radix number of packets per clock cycle without redundant buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional bus-based and crossbar interconnect architectures are used, then system simplicity is maintained, but scalability and performance deteriorate as the number of processing units increases
Solution Approach 1:
The interconnect architecture is segmented into multiple independent NoC switches that can be distributed across the chip. Each switch handles local traffic independently, allowing the system to scale by adding more switches rather than increasing the complexity of a centralized interconnect. This segmentation enables linear scalability with processing units.
Solution Approach 2:
The patent transitions from traditional two-dimensional crossbar architectures to a multi-dimensional NoC topology with multiple routing dimensions. This includes spatial distribution of switches across the chip and logical routing dimensions that provide multiple paths for data flow, enabling scalability without proportionally increasing interconnect complexity.
2Productivity
If the number of processing units increases, then parallel processing capability improves, but delay in supplying instructions and data increases
Solution Approach 1:
The NoC architecture pre-establishes routing paths and uses virtual channels to reserve bandwidth before data transmission begins. This preliminary action prevents congestion and delays by ensuring that routing decisions and resource allocation are made in advance, allowing parallel processing units to receive instructions and data without waiting for dynamic routing negotiations.
Solution Approach 2:
The NoC switches act as intermediaries between processing units and memory systems, buffering and forwarding data packets efficiently. These intermediary switches absorb traffic variations and prevent direct contention between multiple processing units, maintaining low latency even as the number of units increases.
3Reliability
If redundant buffering is implemented to maintain throughput, then data loss is prevented, but on-die area and power consumption increase
Solution Approach 1:
The patent implements buffering capacity that is partial rather than fully redundant. Each NoC switch includes minimal buffering resources sufficient to handle transient congestion and maintain throughput, but not excessive buffering that would consume significant on-die area. This partial buffering approach achieves reliability with reduced area overhead.
Solution Approach 2:
The NoC architecture merges buffering functions into the switch fabric itself rather than implementing separate dedicated buffers for each processing unit or memory interface. This consolidation eliminates redundant buffering resources and reduces total on-die area while maintaining the ability to absorb traffic variations and prevent data loss.
4Area of stationary object
If centralized collapsible queues are used instead of separate input and output queues, then on-die area is reduced, but queue management complexity increases
Solution Approach 1:
The patent implements collapsible queues that dynamically adjust their structure and capacity based on traffic patterns and congestion levels. When congestion is detected, the queue expands to absorb excess packets; when traffic is light, the queue collapses to minimize area usage. This dynamic behavior is controlled by simple expansion and contraction logic that reduces area without requiring complex management overhead.
Solution Approach 2:
The collapsible queue architecture uses self-managing logic that automatically expands and contracts based on internal state and traffic conditions without requiring external control. The queue structure includes built-in detection of congestion states and automatic adjustment of buffer capacity, eliminating the need for complex external queue management while achieving area efficiency.
Data Source
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AI summary
A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.