Network on Chip Design Using Consolidated Traffic Profiles
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Solution Overview
Problem
Current Network on Chip (NoC) interconnect architectures face challenges in efficiently handling multiple traffic profiles and ensuring deadlock-free operation, particularly when different traffic profiles co-exist simultaneously, leading to increased complexity for system designers in determining optimal topology and resource allocation.
Innovation Solution
The proposed solution involves generating a single consolidated traffic profile from individual or subset-based dependency graphs, allowing for the creation of a deadlock-avoidance process and topology design that configures multiple traffic profiles into separate Tx and Rx interface nodes, ensuring they can co-exist without forming deadlocks, and determining bandwidth, latency, and Quality of Service (QoS) requirements for each flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple traffic profiles are handled simultaneously in a NoC interconnect, then the system can support diverse communication requirements, but the complexity of determining optimal topology and resource allocation increases significantly
Solution Approach 1:
The patent segments multiple traffic profiles into distinct subsets, where each subset can be independently analyzed and configured. This segmentation allows designers to handle traffic profiles in manageable groups rather than attempting to optimize all profiles simultaneously, thereby reducing design complexity while maintaining the ability to support diverse communication requirements
Solution Approach 2:
The patent creates a universal topology configuration that can accommodate multiple traffic profile subsets through a standardized interface and resource allocation mechanism. This multi-functional approach allows the same NoC infrastructure to serve different traffic patterns without requiring separate dedicated designs for each profile
2Reliability
If traffic profiles are categorized into subsets for deadlock avoidance, then deadlock-free operation is ensured, but the design process becomes more complex
Solution Approach 1:
The patent applies preliminary action by categorizing traffic profiles into subsets during the design phase before actual operation. This advance classification establishes deadlock avoidance rules and topology configurations proactively, ensuring reliable deadlock-free operation without requiring complex runtime analysis or intervention
3Device complexity
If a consolidated traffic profile is generated from multiple profiles, then resource allocation is simplified, but information about individual profile requirements may be lost
Solution Approach 1:
The patent introduces an intermediary consolidated traffic profile that acts as a mediator between individual traffic profiles and resource allocation mechanisms. This consolidated profile aggregates resource requirements from multiple individual profiles while preserving essential characteristics, enabling simplified resource allocation without complete loss of individual profile information
Data Source
AI summary
The present application is directed to designing an efficient Network on Chip (NoC) interconnect architecture that is adaptable to varied interface protocols of different SoC components/hosts and is compliant to handle different types and models of traffic profiles. Aspects of the present application include a method, which may involve utilizing multiple traffic profiles described in a specification to generate a NoC that satisfies all the traffic profiles. Such a NoC interconnect architecture can be formed from multiple traffic profiles by generating a single consolidated traffic profile from individual or subset based dependency graphs of the multiple traffic profiles.