NoC Sub-Topology Coupling With DPLL-Derived Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bus architectures in system-on-chip (SoC) designs face challenges with finite wire delay and shared bus contention, leading to performance limitations and synchronization issues as chip size and density increase, which are not adequately addressed by network-on-chip (NoC) technology.
Innovation Solution
Implementing digital phase locked loops (DPLLs) to couple network-on-chip sub-topologies, allowing for the generation of derivative clocks that synchronize data transmission across sub-topologies, thereby reducing long wire paths and RC delays through the use of interfacing blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional bus architectures are used in SoC designs, then device complexity is reduced, but wire delay and bus contention increase leading to performance limitations
Solution Approach 1:
The patent divides the NoC into multiple sub-topologies (e.g., first sub-topology, second sub-topology) that can operate independently with different clock frequencies. This segmentation allows each sub-topology to be optimized separately, reducing overall communication delay while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent implements dynamic clocking where different sub-topologies can operate at different clock frequencies simultaneously. The DPLL circuits dynamically generate derivative clocks tailored to specific sub-topology requirements, enabling flexible speed optimization without requiring a unified slow clock across the entire NoC.
2Device complexity
If a unified clock is used across the entire NoC, then device complexity is reduced, but timing synchronization becomes difficult for large chips
Solution Approach 1:
The clock distribution system is segmented into multiple independent DPLL circuits, each serving a specific sub-topology. This eliminates the need for a single unified clock tree across the entire chip, reducing the complexity of clock routing while ensuring reliable timing synchronization within each sub-topology through localized phase-locked loops.
Solution Approach 2:
DPLL circuits act as intermediary devices between the source clock and the sub-topologies. Each DPLL receives a reference clock and generates a derivative clock that is phase-synchronized to the sub-topology's timing requirements, mediating the timing relationship between different sub-topologies without requiring direct clock distribution across the entire chip.
3Productivity
If sub-topologies operate at different clock frequencies, then communication efficiency is improved, but interface complexity between sub-topologies increases
Solution Approach 1:
DPLL circuits serve as intermediary synchronization devices at the interfaces between sub-topologies. When data transfers between sub-topologies operating at different frequencies, the DPLL generates derivative clocks that maintain phase relationships, enabling efficient frequency conversion and timing alignment without complex interface control logic.
Solution Approach 2:
The system changes the clock frequency parameter dynamically based on the specific sub-topology requirements. Each sub-topology can operate at its optimal frequency while the DPLL interfaces handle the parameter transformation between different frequency domains, maintaining communication efficiency without requiring uniform clock parameters across all interfaces.
4Area of stationary object
If long wire paths are used to connect distant logic blocks, then area utilization is improved, but RC delays increase reducing performance
Solution Approach 1:
The patent applies dynamic clocking with DPLL circuits to compensate for the RC delays inherent in long wire paths. By generating derivative clocks locally at each sub-topology and using them for data synchronization, the system can tolerate longer wire paths without performance degradation, as the local clocks absorb the timing variations caused by long interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances SoC performance by synchronizing data transmission between sub-topologies, reducing timing issues and improving communication speed and efficiency, even when sub-topologies operate at different clock frequencies.
Implementation Method 1
The first DPLL generates a second clock, wherein the generating includes saving, by the interfacing block, the data that was sent
Data Source
AI summary
Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.