Network-on-Chip Data Communication Network with Cycle-Aligned Delay Elements
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in maintaining high clock speeds due to slow communication channels, particularly when data with varying cycle lengths are communicated, as introducing delays in these channels can cause routing information to arrive outside designated cycles, leading to erroneous behavior in network-on-chip (NoC) designs.
Innovation Solution
The introduction of M*N data storage elements into the slowest communication channel to introduce a delay of M*N cycles, ensuring that data packages are received during the appropriate cycle by aligning the communication delay with the periodicity of network stations, and using phase shifting techniques to maintain correct routing information evaluation phases across the network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If M*N data storage elements are introduced into the slowest communication channel to increase clock speed, then the data communication speed is improved, but the routing information may arrive outside the predefined clock cycle causing erroneous network behavior
Solution Approach 1:
The data package is segmented into N data elements, with routing information contained in the first data element. The communication channel is segmented into N subchannels, each handling one data element. This segmentation allows the routing information to be transmitted separately and synchronously with the clock cycles, ensuring that even with added delay elements, the routing information arrives at the correct predefined clock cycle while other data elements can be delayed to match the slowest channel speed.
2Reliability
If delays are introduced in communication channels to match the periodicity of network stations, then the correct phase relations are maintained, but the latency of data transmission increases
Solution Approach 1:
Different subchannels are assigned different numbers of delay elements based on their specific delay characteristics. The first subchannel (carrying routing information) receives a specific number of delay elements to align with clock cycles, while other subchannels receive delay elements proportional to their relative delay compared to the first subchannel. This local customization ensures each subchannel is optimized for its specific timing requirements rather than applying a uniform delay to all channels.
3Power
If the clock speed is increased to improve processing capacity, then the data processing capability is improved, but the slowest communication channel becomes the bottleneck determining the maximum operating speed
Solution Approach 1:
Data storage elements (latches or flip-flops) are introduced as intermediary components in the slowest communication channel. These storage elements act as buffers that decouple the clock speed of the network from the propagation delay of the communication channel. The storage elements hold the data package elements until the next clock cycle, allowing the network to operate at higher clock speeds without being constrained by the physical delay of the slowest channel.
Data Source
AI summary
An integrated circuit includes functional blocks and a data communication network having network stations interconnected via communication channels for communicating data packages between the functional blocks. Each data package includes N data elements having a data element with routing information for the network stations, N being an integer of at least two. The network stations include data routers and network interfaces, where each of the data routers is coupled to a functional block via a network interface. The data communication network includes first and second network stations interconnected through a first communication channel. The network includes M*N data storage elements, M being a positive integer, for introducing a delay of M*N cycles on the first communication channel.