Network-on-Chip with Deterministic Routing for Multi-Core Latency
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Solution Overview
Problem
Current multi-core processor architectures face challenges with cache coherence and virtual memory addressing, leading to increased power consumption, latency, and complexity due to the use of cache hierarchies and memory management units.
Innovation Solution
A network-on-chip architecture is introduced, eliminating cache hierarchies and memory management units by using scratchpad memories and routers with a deterministic static priority routing policy, allowing direct communication between processor cores and minimizing memory access bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache hierarchies and memory management units are used in multi-core processor architectures, then data storage and memory management capabilities are improved, but power consumption, latency, and system complexity increase
Solution Approach 1:
The patent extracts and removes the cache hierarchy and memory management units from the multi-core processor architecture. Each core is directly connected to a unified memory space through a network-on-chip, eliminating the need for complex cache coherence protocols and memory management hardware, thereby reducing power consumption while maintaining data storage capability
Solution Approach 2:
The patent implements a unified memory space that is universally accessible by all processor cores through the network-on-chip. This shared memory architecture replaces the traditional separate cache memories in each core, providing a universal data storage resource that reduces overall system complexity and power consumption while maintaining accessibility for all cores
2Reliability
If cache hierarchies are used in multi-core processor architectures, then data storage capability is improved, but access latency increases
Solution Approach 1:
The patent removes the multi-level cache hierarchy that introduces access latency. Instead, it provides direct access to a unified memory space from all processor cores through the network-on-chip, eliminating cache lookup delays and coherence protocol overhead while maintaining data storage capability
Solution Approach 2:
The patent pre-establishes a direct communication path between all processor cores and the unified memory space through the network-on-chip architecture. This preliminary structural arrangement eliminates the need for dynamic cache management and coherence protocols during runtime, reducing access latency while maintaining data storage reliability
3Reliability
If cache hierarchies and memory management units are used, then data storage and management capabilities are improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex cache hierarchy and memory management units from each processor core. The unified memory space accessed through the network-on-chip provides data storage capability without requiring complex cache coherence protocols, address translation hardware, and memory management units, thereby reducing system complexity
Solution Approach 2:
The patent implements a universal unified memory space that serves all processor cores through the network-on-chip. This single shared memory resource replaces multiple separate cache memories and memory management units, providing data storage capability while significantly reducing overall system complexity through consolidation
4Productivity
If deterministic static priority routing policy is implemented in network-on-chip, then data routing efficiency and latency guarantee are improved, but routing policy complexity increases
Solution Approach 1:
The patent pre-establishes a deterministic static priority routing policy in the network-on-chip architecture. Routing priorities are assigned to different data traffic types and destinations in advance, allowing routers to make deterministic forwarding decisions without complex runtime analysis, thereby improving data routing efficiency and latency guarantee while keeping the routing policy manageable
Data Source
AI summary
A method and system including a set of processor cores; and a set of routers each including a set of input ports and a set of output ports, where: each processor core of the set of processor cores corresponds to a different router of the set of routers and is communicatively coupled with a corresponding router via the router's set of input ports and set of output ports, based on a physical destination address of a data packet, each router is operable to send one or more data packets to the one or more adjacent routers or the processor core corresponding to the router, where each router is operable to retain a data packet in the event of a traffic condition, and each router implements a deterministic routing policy.