Network-on-Chip Performance Characterization via Dynamic Routing

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Solution Overview

Problem

The increasing complexity and component count on System-on-Chip (SoC) and Network-on-Chip (NoC) architectures pose challenges in characterizing performance under varying traffic conditions, leading to potential bottlenecks and inefficiencies in communication due to limitations in traditional interconnect architectures.

Innovation Solution

The implementation of methods and systems for automatically characterizing the performance of SoC and NoC in terms of latency and throughput by simulating traffic profiles with varying load levels, measuring performance attributes, and generating graphs to identify optimal and critical conditions, allowing for the identification of congested channels and agents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional buses and crossbar based interconnects are used, then implementation is simpler, but scalability is limited

Engineering Contradiction:
Improveinterconnect implementation complexityVSAvoidscalability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The interconnect is segmented into multiple routing nodes connected by point-to-point physical links, forming a Network-on-Chip architecture that replaces the monolithic traditional bus or crossbar structure. This segmentation enables scalable expansion by adding more routing nodes and links without fundamentally changing the interconnect paradigm.

Inventive Principle:
Principle #1Segmentation

2Reliability

If deterministic routing is used, then packet ordering is maintained and deadlocks are avoided, but load balancing across path diversities is not achieved

Engineering Contradiction:
Improvepacket ordering and deadlock freedomVSAvoidload balancing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The routing system dynamically selects paths based on network state and traffic conditions rather than using fixed deterministic paths. This dynamic routing enables load balancing across multiple path diversities while maintaining reliability through adaptive decision-making at each routing node.

Inventive Principle:
Principle #15Dynamics

3Loss of time

If shortest path routing is used, then latency is minimized, but network congestion on specific paths may increase

Engineering Contradiction:
Improvecommunication latencyVSAvoidnetwork congestion resistance
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The routing system changes path selection parameters dynamically based on network conditions, traffic patterns, and congestion levels. Instead of always selecting the shortest path, the system adjusts routing decisions to distribute traffic across multiple paths, reducing congestion while maintaining acceptable latency through adaptive parameter optimization.

Inventive Principle:
Principle #35Parameter changes

4Measurement precision

If performance characterization is performed manually, then detailed analysis is possible, but the process is time-consuming and inefficient

Engineering Contradiction:
Improveperformance analysis detailVSAvoidcharacterization time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The NoC interconnect performs self-characterization by automatically monitoring its own performance metrics, traffic patterns, and operational parameters. This self-service approach enables detailed performance analysis without external manual intervention, significantly reducing characterization time while maintaining measurement precision through built-in sensing and reporting capabilities.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10528682B2Automatic performance characterization of a network-on-chip (NOC) interconnect
Publication Date: 2020.01.07 INTEL CORP
  • US10528682B2 patent drawing
  • US10528682B2 patent drawing
  • US10528682B2 patent drawing

AI summary

Methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a System-on-Chip (SoC) and/or Network-on-Chip (NoC) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve a plot representative of latency and throughput, depending on the desired implementation.