NoC-Fabric Routing With Shared Multiplexers to Ease IC Congestion
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Solution Overview
Problem
Configurable integrated circuits face inefficiencies due to underutilization of network-on-chip (NOC) and fabric routing resources, as they are sized for worst-case scenarios, leading to unused IC die area and congestion.
Innovation Solution
A hybrid network-on-chip (NOC) configurable fabric routing architecture that shares a set of routing conductors, using switch and multiplexer circuits to optimize signal routing, reducing congestion by bypassing portions of the NOC and fabric routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NOC and fabric routing are sized for worst-case scenarios, then reliability is improved, but device complexity and IC die area increase
Solution Approach 1:
The patent merges the NOC routing resources with fabric routing resources by allowing fabric regions to bypass the NOC structure. Shared routing conductors are used for both NOC and fabric routing, eliminating the need for separate dedicated wiring for worst-case scenarios. This consolidation reduces overall device complexity while maintaining reliability through dynamic resource allocation.
Solution Approach 2:
The invention introduces dynamic routing capability where the system can adaptively switch between NOC routing and fabric routing based on actual traffic conditions. Multiplexer circuits enable dynamic selection of routing paths, allowing the system to optimize resource utilization in real-time rather than being statically sized for worst-case scenarios.
2Reliability
If the NOC and fabric routing are sized for worst-case scenarios, then reliability is improved, but IC die area increases
Solution Approach 1:
The patent merges the NOC routing resources with fabric routing resources by allowing fabric regions to bypass the NOC structure. Shared routing conductors are used for both NOC and fabric routing, eliminating the need for separate dedicated wiring for worst-case scenarios. This consolidation reduces overall device complexity while maintaining reliability through dynamic resource allocation.
Solution Approach 2:
The invention makes routing conductors universal by designing them to serve multiple functions: they can be used for NOC routing, fabric routing, or both simultaneously through the bypass mechanism. This multi-functionality eliminates the need for dedicated worst-case routing resources, reducing IC die area while maintaining reliability.
3Adaptability or versatility
If dedicated routing resources are allocated for NOC and fabric routing, then routing capability is improved, but resource utilization efficiency deteriorates
Solution Approach 1:
The invention introduces dynamic routing capability where the system can adaptively switch between NOC routing and fabric routing based on actual traffic conditions. Multiplexer circuits enable dynamic selection of routing paths, allowing the system to optimize resource utilization in real-time rather than being statically sized for worst-case scenarios.
Solution Approach 2:
The routing system serves itself by allowing fabric regions to bypass the NOC structure and use shared routing conductors directly. This self-service mechanism enables the routing infrastructure to dynamically allocate resources based on actual needs rather than requiring dedicated reserved capacity, improving overall resource utilization efficiency.
Data Source
AI summary
An integrated circuit includes a central region having first multiplexer circuits and first busses that interconnect the first multiplexer circuits. The integrated circuit also includes a network-on-chip. The network-on-chip includes switch circuits, second multiplexer circuits, second busses that interconnect the switch circuits, third busses that interconnect the switch circuits and the second multiplexer circuits, and fourth busses that interconnect the first multiplexer circuits and the second multiplexer circuits. Each of the second multiplexer circuits is coupled to at least two of the switch circuits through a subset of the third busses.


