NoC Fault Detection Tool for Memory Protection and Deadlock Avoidance
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Solution Overview
Problem
The design of network-on-chip (NoC) systems is complex and time-consuming, requiring frequent revisions due to changes in performance requirements or chip floorplans, and lacks efficient methods for fault detection and classification in memory protection, leading to challenges in deadlock avoidance and reuse of existing topologies.
Innovation Solution
A tool is developed to efficiently generate and synthesize NoC systems by classifying faults related to memory protection, reducing the number of bits used, and incrementally designing the NoC one connection at a time, while ensuring deadlock-free operation and minimizing power and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional NoC design methods are used, then design flexibility and adaptability are maintained, but design time and complexity increase significantly
Solution Approach 1:
The patent segments the NoC design process into distinct phases: topology generation, routing algorithm selection, and deadlock avoidance verification. This segmentation allows each phase to be optimized independently, reducing overall design time while maintaining flexibility. The topology generation phase uses automated algorithms to create candidate topologies, the routing phase selects appropriate algorithms, and the verification phase checks for deadlock conditions, enabling systematic and efficient design iteration.
Solution Approach 2:
The patent applies preliminary action by pre-defining a library of deadlock-free routing algorithms and topology patterns before the actual design process. These pre-characterized building blocks can be directly applied to new designs without requiring complete redesign, significantly reducing design time while maintaining adaptability to different performance requirements.
2Adaptability or versatility
If frequent design revisions are made to meet changing requirements, then adaptability is improved, but productivity decreases due to repeated work
Solution Approach 1:
The patent implements dynamics by creating a parametric NoC design system where topology parameters, routing algorithm parameters, and performance constraints can be dynamically adjusted without restarting the entire design process. The system maintains a database of design configurations and can efficiently transition between different parameter sets, allowing frequent requirement changes to be accommodated with minimal rework.
Solution Approach 2:
The patent uses copying by maintaining a repository of validated NoC topology templates and routing configurations. When new design requirements arise, the system can copy and adapt existing validated configurations rather than creating designs from scratch, ensuring consistency and reducing the impact of revisions on productivity.
3Reliability
If comprehensive fault detection and classification is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by implementing a unified fault classification framework that handles multiple types of memory faults (bit flips, stuck-at faults, transient faults) through a single classification mechanism. This universal classifier uses a standardized set of features and decision rules that work across different memory structures and fault types, improving reliability without proportionally increasing complexity.
Solution Approach 2:
The patent uses parameter changes by implementing a configurable fault detection system where the level of scrutiny and classification detail can be adjusted based on application requirements. Critical memory regions can be monitored with higher precision, while less critical regions use lighter monitoring, allowing comprehensive fault detection to be tuned to match actual reliability needs and minimize unnecessary complexity.
4Adaptability or versatility
If incremental NoC synthesis is used to add new connections, then adaptability is improved, but manufacturing precision challenges arise from reusing existing topology
Solution Approach 1:
The patent implements feedback by incorporating verification steps that check whether incremental topology modifications maintain deadlock-free properties and meet performance constraints. After each incremental addition or modification of connections, the system verifies the updated topology against predefined criteria and adjusts parameters if violations are detected, ensuring manufacturing precision is maintained throughout the evolution process.
Solution Approach 2:
The patent applies preliminary anti-action by performing preliminary checks and validations before implementing incremental topology changes. The system evaluates potential modifications against deadlock conditions and performance constraints in advance, preventing invalid changes from being applied and thus avoiding precision issues that would require corrective rework.
Data Source
AI summary
System and methods are implemented by a tool used in generation and synthesis of networks, such as a network-on-chip (NoC). The tool includes an algorithm that identifies and classifies faults and thereby results in efficiency in determination of the cause of the fault. The tool allows a designer or user to provide solutions or make edits as needed to address the cause of the fault.