NoC Floorplan Guidance for Timing-Aware Topology Synthesis
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Solution Overview
Problem
Designing an optimal network-on-chip (NoC) that meets performance, timing, power, and area constraints is challenging due to the lack of physical floorplan information, leading to difficulties in implementing communication between components that are logically adjacent but physically far apart, resulting in production delays and inefficiencies.
Innovation Solution
A method and system for generating NoC implementation guidance using constraints and inputs to place elements on a chip floorplan, which includes augmenting the NoC with information to meet performance criteria and providing timing estimation to determine component distances, allowing for the insertion of distance pipes to address timing requirements while optimizing performance, bandwidth, and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If NoC elements are placed based on logical adjacency without physical floorplan information, then the design process is simpler, but timing requirements cannot be met when components are physically far apart
Solution Approach 1:
The system performs preliminary timing estimation during the NoC synthesis phase, before physical implementation, by using augmented floorplan information to predict timing requirements. This allows the synthesis tool to generate appropriate timing constraints and guidance upfront, preventing timing violations in downstream implementation tools.
Solution Approach 2:
The patent introduces an intermediary mechanism that augments the floorplan with timing-related information and uses this augmented data to generate timing constraints. This intermediary layer bridges the gap between logical NoC design and physical timing requirements, enabling timing-aware synthesis without requiring complete physical floorplan details.
2Reliability
If distance pipes are inserted to meet timing requirements, then timing constraints are satisfied, but latency increases due to additional clock cycles
Solution Approach 1:
The system applies partial action by selectively inserting distance pipes only where timing requirements are violated, rather than uniformly across all connections. The timing estimation identifies specific problematic connections, and distance pipes are inserted only for those cases, minimizing the overall impact on latency while satisfying timing constraints where necessary.
Solution Approach 2:
The system uses feedback from timing estimation results to guide the insertion of distance pipes. The timing estimation provides information about which connections exceed timing requirements, and this feedback drives the selective placement of distance pipes to correct only those specific timing violations, optimizing the balance between timing satisfaction and latency minimization.
3Adaptability or versatility
If the NoC design is revised frequently to accommodate changing requirements, then the design adapts to new constraints, but production delays occur due to repeated redesign
Solution Approach 1:
The system performs preliminary timing estimation and generates timing constraints during the initial synthesis phase, before physical implementation. This preliminary action creates a robust foundation that can accommodate requirement changes more efficiently, as the timing-aware synthesis framework can be re-executed with new parameters without requiring complete redesign.
Solution Approach 2:
The system enables dynamic adaptation by allowing the synthesis process to be re-executed with updated requirements. The timing estimation and constraint generation are performed dynamically based on current design parameters, floorplan information, and performance targets, allowing the design to adapt to changing requirements without rigid restructuring.
Data Source
AI summary
System and methods are disclosed for augmenting a synthesized NoC, with data that guides a physical implementation of the NoC topology in a way that coincides with the topology synthesis result and reduces timing violations in the final physical design. The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC. The system inserts a link as a pipeline placeholder and a minimum set of created module regions are assigned to a specific link of the topology. Each route has a new link and corresponding module region inserted into the physical path.