NoC Flow Control Synchronization Across Multiple Clock Domains

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Solution Overview

Problem

Current Network-on-Chip (NoC) architectures face scalability limitations due to synchronization issues with clock signals, particularly in distributed architectures where distributing a single clock signal is costly in terms of time and area, and asynchronous designs incur significant overhead in wires and latency.

Innovation Solution

The system employs a synchronization mechanism using latch circuits and bisynchronous memory to synchronize control signals between transmitter and receiver modules, allowing data transmission across modules clocked with differing frequencies, eliminating the need for a single clock signal across the entire NoC structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a single clock signal is distributed across the entire NoC structure, then synchronization is achieved, but time cost and area increase due to buffers needed to overcome phase shifting

Engineering Contradiction:
ImprovesynchronizationVSAvoidarea
Core Design Contradiction:
Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

The patent divides the NoC into multiple clock domains, each with its own clock signal. Instead of using a single global clock, the system segments the clock distribution into local clock regions (first clock domain and second clock domain), eliminating the need for extensive buffer networks across the entire chip.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a synchronization mechanism using control signals and latch circuits as intermediaries between different clock domains. The control signals mediate the interaction between modules operating on different clocks, allowing data transfer without requiring direct clock distribution across the entire NoC.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If buffers are added to overcome phase shifting in different areas, then synchronization is maintained, but time cost increases

Engineering Contradiction:
ImprovesynchronizationVSAvoidtime
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

By segmenting the NoC into multiple clock domains with local clocks, the patent eliminates the need for long-distance clock distribution and associated buffers, thereby reducing the time delays inherent in global clock synchronization approaches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The synchronization mechanism performs preliminary actions by using control signals to coordinate data transfer between clock domains before actual data movement occurs. This allows the system to prepare for cross-clock-domain transfers in advance, avoiding time-consuming synchronization delays during runtime.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If asynchronous communication is used, then clock distribution issues are resolved, but overhead in wires and area increases significantly

Engineering Contradiction:
Improveclock domain compatibilityVSAvoidcomplexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by allowing different regions of the NoC to have different clock characteristics (different frequencies and phases). Each clock domain maintains its own timing characteristics locally, while the synchronization mechanism ensures proper coordination at the boundaries between domains.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The control signals and latch circuits serve as intermediaries that enable communication between different clock domains without requiring full asynchronous communication infrastructure. This mediator approach reduces the wire overhead and area complexity compared to traditional asynchronous designs.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Ease of operation

If traditional synchronous protocols are used, then simple communication is achieved, but scalability is limited due to synchronization issues

Engineering Contradiction:
Improvecommunication simplicityVSAvoidscalability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent segments the communication system into multiple clock domains that can operate independently with different timing characteristics. This segmentation allows the NoC to scale to larger sizes and higher frequencies without being constrained by a single global clock, while maintaining simple synchronous communication protocols within each domain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adapts to different clock domains by using control signals that can accommodate varying clock frequencies and phases. This dynamic approach allows the NoC to scale flexibly, adding modules with different timing characteristics without requiring a complete redesign of the communication infrastructure.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7861018B2System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link
Publication Date: 2010.12.28 STMICROELECTRONICS FRANCE
  • US7861018B2 patent drawing
  • US7861018B2 patent drawing

AI summary

A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.