Network-on-Chip Placement and Routing via Integer Linear Programming
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Solution Overview
Problem
In network-on-chip (NOC) implementations for integrated circuits, existing methods often prioritize one competing interest over others, leading to sub-optimal solutions due to sequential placement and routing approaches that do not consider multiple independent interests concurrently.
Innovation Solution
The use of integer linear programming (ILP) to simultaneously generate placement and routing constraints for nets within a programmable NOC, allowing for concurrent mapping of logical units to interface circuits and channels while minimizing an objective function, thereby addressing independent interests such as latency and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential placement and routing approaches are used to address competing interests independently, then the implementation process becomes simpler and more manageable, but the solution quality deteriorates due to sub-optimal results
Solution Approach 1:
The patent combines placement and routing operations into a single simultaneous process using integer linear programming. Instead of performing placement first and then routing separately, both operations are formulated as concurrent optimization problems that share common constraints and objectives, allowing the system to find globally optimal solutions that satisfy multiple competing interests (latency, bandwidth, power) without the sub-optimal results of sequential approaches.
2Manufacturing precision
If multiple competing interests are addressed simultaneously using ILP, then solution quality improves by considering all interests concurrently, but the computational complexity and problem difficulty increase
Solution Approach 1:
The patent transforms the placement and routing problem into an integer linear programming formulation by defining specific parameters and variables. It introduces binary variables to represent placement decisions and routing path selections, and formulates constraints in terms of linear equations that capture latency requirements, bandwidth limitations, and power consumption targets. This parameter transformation allows sophisticated multi-objective optimization while maintaining a structured computational approach that can be solved using standard ILP solvers.
3Ease of operation
If conventional sequential approaches are used, then the design process is easier to manage and implement, but deadlock conditions may be introduced that require additional removal steps
Solution Approach 1:
The patent performs preliminary deadlock prevention by formulating routing constraints that explicitly prevent cyclic dependencies before the actual routing occurs. The ILP formulation includes constraints that ensure acyclic routing paths and proper resource allocation ordering, thereby preventing deadlocks from occurring in the first place. This eliminates the need for separate deadlock detection and removal steps that would be required after conventional sequential routing.
Data Source
AI summary
Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.