NoC Interposer with Binary Port Weights for QoS Isolation
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Solution Overview
Problem
Systems on a Chip (SoCs) face challenges in energy efficiency and bandwidth management due to capacitive and resistive loading issues in traditional bus-type systems, leading to timing and power consumption problems, and conventional inter-process communication methods are inefficient and error-prone, especially for data transport and synchronization across multiple cores.
Innovation Solution
A network-on-chip (NoC) system with interposers that assign binary port weights and use traversal counters and masks to manage data transmission, offloading core cycles and ensuring quality of service (QoS) by balancing data traffic and minimizing head-of-line blockages, while using autonomic transport blocks for efficient message-passing and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional bus-type systems are used for communication between endpoints, then device complexity is reduced, but energy consumption increases and timing problems occur due to capacitive and resistive loading
Solution Approach 1:
The patent segments the traditional bus-type interconnect into multiple point-to-point connections through a network-on-chip architecture. Instead of a single shared bus, data travels through dedicated routed paths between endpoints, eliminating capacitive and resistive loading issues while reducing energy consumption.
2Device complexity
If traditional bus-type systems are used for communication, then device complexity is reduced, but timing problems occur due to capacitive and resistive loading
Solution Approach 1:
The patent divides the monolithic bus into segmented routed paths, where each connection has controlled impedance and timing characteristics. This segmentation allows for proper signal timing and eliminates the timing problems associated with traditional bus structures.
3Use of energy by moving object
If NoC interconnect is implemented to improve energy efficiency and QoS, then energy consumption is reduced and bandwidth control is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic bandwidth allocation and QoS control mechanisms in the NoC, allowing the system to adapt traffic routing and resource allocation based on real-time demands. This dynamic control optimizes energy efficiency while managing the complexity through intelligent resource management.
4Ease of operation
If conventional IPC methods are used for data transport between cores, then ease of operation is maintained, but productivity decreases due to core cycle overhead and errors
Solution Approach 1:
The patent introduces an autonomic transport block as an intermediary between cores, handling data transport, buffering, and synchronization operations. This mediator offloads productivity-critical tasks from the cores themselves, enabling efficient message passing without compromising ease of operation.
5Ease of operation
If one-sided DMA is used for data movement, then ease of operation is improved, but reliability decreases due to complexity and errors in managing entire SoC address space
Solution Approach 1:
The autonomic transport block serves as a reliable intermediary that manages data movement between memory spaces. It handles address translation, buffering, and error checking, providing reliable data transport while maintaining ease of operation through simplified interface configuration.
Data Source
AI summary
Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.