Network-on-Chip Interposer for Modular IC Scalability
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Solution Overview
Problem
Monolithic FPGA SoC designs face limitations in scalability and fabrication efficiency due to restricted shoreline integration of peripheral IPs, leading to reduced performance and increased costs, with high latency and limited bandwidth connectivity between dies.
Innovation Solution
A modularized integrated circuit approach with a network-on-chip (NOC) interface integrated into a silicon interposer, enabling high-bandwidth, low-latency connectivity through routers and microbumps, allowing independent design and fabrication of peripheral IP and programmable fabric dies, and facilitating scalable and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If monolithic FPGA SoC designs integrate peripheral IPs on shoreline, then device functionality is provided, but scalability is limited and fabrication efficiency decreases
Solution Approach 1:
The patent divides the integrated circuit into multiple independent dies: a first die containing logic elements and a second die containing peripheral intellectual property cores. These separate dies are fabricated independently and then interconnected through a silicon interposer with embedded network-on-chip interfaces and microbumps, enabling modular scalability while simplifying fabrication processes for each individual die.
2Speed
If peripheral IPs are integrated on shoreline of programmable fabric, then device functionality is achieved, but connectivity bandwidth is limited and latency increases
Solution Approach 1:
The patent introduces a silicon interposer as an intermediary substrate that hosts network-on-chip interfaces and establishes high-speed interconnects between the logic elements die and peripheral IPs die. This intermediary structure enables parallel data paths and reduces communication latency compared to traditional shoreline integration methods.
Solution Approach 2:
The patent transitions from two-dimensional shoreline integration to a three-dimensional stacked architecture where logic elements and peripheral IPs are placed on separate dies vertically interconnected through the silicon interposer. This dimensional change enables higher bandwidth connectivity through multiple parallel microbump interconnects.
3Adaptability or versatility
If modularized dies are used with microbumps for interconnection, then scalability is improved, but microbump overhead and silicon area consumption increase
Solution Approach 1:
The silicon interposer is designed as a universal platform that can accommodate different configurations of logic elements dies and peripheral IPs dies. The network-on-chip interfaces and microbump patterns are standardized to enable flexible interconnection topologies, allowing the same interposer structure to support various device configurations without proportionally increasing silicon area consumption.
Data Source
AI summary
Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.