NoC IP Core Placement for Latency Optimization

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Solution Overview

Problem

In Network-on-Chip (NoC) interconnects, the optimization of heterogeneous SoC IP core placement is challenging due to scalability limitations and non-uniform traffic patterns, leading to suboptimal system performance in terms of latency, bandwidth, and connectivity, especially in complex System-on-Chips with diverse components and communication requirements.

Innovation Solution

An automated method for determining the optimal positions of heterogeneous IP cores of different shapes and sizes within a mesh or Taurus NoC interconnect, ensuring efficient connectivity and minimizing spatial overlap while configuring NoC routers and paths to optimize latency, bandwidth, and distance between communicating hosts, using heuristic approaches to address the NP-hard optimization problem.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional bus or crossbar interconnects are used, then simple connectivity is achieved, but scalability is limited

Engineering Contradiction:
ImprovescalabilityVSAvoidinterconnect complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The interconnect is segmented into multiple NoC domains, each handling specific traffic patterns. This segmentation allows the system to scale by adding more domains without increasing the complexity of each individual domain, resolving the contradiction between scalability and complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the interconnect architecture, organizing NoC domains in multiple levels. This dimensional change enables scalability by allowing the system to grow vertically through hierarchy rather than horizontally through flat expansion, which would increase complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If deterministic routing is used, then packet ordering is maintained, but load balancing across path diversities is not achieved

Engineering Contradiction:
Improvepacket orderingVSAvoidload balancing
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The routing system dynamically selects between deterministic and load-balancing strategies based on current network conditions. This dynamic approach allows the system to maintain packet ordering when needed while achieving load balancing during normal operation, resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes routing parameters dynamically, switching between different routing algorithms based on traffic patterns and network state. This parameter change enables the system to optimize for either packet ordering or load balancing depending on current requirements, resolving the contradiction.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If shortest path routing is used, then latency is minimized, but network congestion on specific paths occurs

Engineering Contradiction:
Improvecommunication latencyVSAvoidnetwork congestion
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent uses partial shortest path routing, where only critical time-sensitive traffic uses the shortest path while other traffic uses alternative routes. This partial application of shortest path routing minimizes latency for important traffic while avoiding congestion on heavily used paths, resolving the contradiction.

Inventive Principle:
Principle #16Partial or excessive action

4Productivity

If manual IP core placement is performed, then placement flexibility is maintained, but optimization of latency and interconnect performance is suboptimal

Engineering Contradiction:
Improveinterconnect performanceVSAvoidplacement optimization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs automated IP core placement optimization using algorithms that evaluate multiple placement scenarios and select the optimal configuration. This self-service approach eliminates the need for manual optimization while achieving superior latency and performance metrics, resolving the contradiction between productivity and complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10554496B2Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
Publication Date: 2020.02.04 INTEL CORP
  • US10554496B2 patent drawing
  • US10554496B2 patent drawing
  • US10554496B2 patent drawing

AI summary

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.