Network-on-Chip Link Delay Routing via Tunable Replica Circuits

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Solution Overview

Problem

Current Network-on-Chip (NoC) routing algorithms do not effectively account for process/voltage/temperature (PVT) variations and aging-induced link delays, leading to performance and energy efficiency issues in on-die data communications.

Innovation Solution

The implementation of tunable replica circuits (TRCs) per link or group of links to track and calibrate PVT variations and aging effects, providing delay information for intelligent routing algorithms to optimize traffic routing and improve performance, throughput, and energy efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional routing algorithms are used in NoC, then device complexity is reduced, but performance and energy efficiency deteriorate due to unaccounted PVT variations and aging effects

Engineering Contradiction:
ImprovethroughputVSAvoidrouting algorithm complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing delay calibration before runtime operations. Tunable replica circuits are calibrated to measure link delays under various PVT conditions, and this calibration data is stored for use during runtime routing decisions, avoiding the need for complex real-time measurements

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating tunable replica circuits that replicate the actual link characteristics. These replica circuits copy the delay properties of physical links and can be tuned to match different operating conditions, allowing routing decisions to be made based on modeled rather than direct measured delays

Inventive Principle:
Principle #26Copying

2Reliability

If link delay variations are not accounted for, then device complexity is minimized, but reliability deteriorates due to increased errors and latency

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidrouting control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback by continuously monitoring link delays through tunable replica circuits and using this information to adjust routing decisions. The system feeds back delay measurements and uses this information to select optimal paths, improving reliability through adaptive routing

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting routing parameters based on measured delay variations. The system changes route selections and transmission parameters in response to PVT variations and aging effects, maintaining reliable data transmission despite changing conditions

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3238388B1Link delay based routing for a network-on-chip
Publication Date: 2021.06.09 INTEL CORP
  • EP3238388B1 patent drawingFigure 1
  • EP3238388B1 patent drawingFigure 2
  • EP3238388B1 patent drawingFigure 3

AI summary

A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information. The delay information is obtained from a plurality of tunable replica circuits, a tunable replica circuit to track delay through one or more of the plurality of links.