NoC Link Sideband Serialization for Lower Wire Count
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Solution Overview
Problem
Existing Network-on-Chip (NoC) technologies face inefficiencies in transporting header and payload flits due to the need for wider and multiple wires, leading to increased power consumption, complexity, and manufacturing costs.
Innovation Solution
Implementing a serializer and deserializer within the NoC to serialize the header and payload flits for transmission through a transport link, followed by deserialization at the destination, reducing the number of wires required and optimizing power consumption and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If header and payload flits are transmitted in parallel through multiple wires, then transmission speed is improved, but power consumption and manufacturing cost increase
Solution Approach 1:
The patent implements serial transmission where header and payload flits are sent sequentially through the same physical wire over time. The header is transmitted first, followed by the payload flits in sequence. This periodic/sequential action reduces simultaneous wire usage while maintaining acceptable transmission throughput through proper timing and clock cycle management.
Solution Approach 2:
The patent uses a single physical wire to carry multiple logical channels of data (header channel and payload channel) by transmitting them at different time periods. This time-division multiplexing allows one physical medium to serve multiple logical purposes, reducing the total number of wires needed while maintaining full communication functionality.
2Productivity
If header and payload flits are transmitted in parallel through multiple wires, then bandwidth utilization is improved, but manufacturing cost increases
Solution Approach 1:
The same physical wire is designed to handle multiple functions: transmitting headers, transmitting payload data, and supporting multiple virtual channels. By making the transmission medium universal and multi-functional through time-division multiplexing, the patent reduces the total quantity of wires needed, directly lowering manufacturing cost while maintaining bandwidth capacity.
Solution Approach 2:
The system uses periodic time-division multiplexing where different data types (header vs. payload) and different virtual channels are transmitted in alternating time slots over the same wire. This periodic action allows one wire to replace multiple dedicated wires, reducing manufacturing complexity and cost.
3Reliability
If multiple physical channels are used for transmitting header and payload flits, then transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces serialization/deserialization logic as an intermediary mechanism that manages the transmission of header and payload flits sequentially through a single wire. This intermediary control logic ensures proper timing, synchronization, and error handling, maintaining transmission reliability while avoiding the complexity of multiple parallel physical channels.
Solution Approach 2:
The system uses periodic clock cycles and time-division multiplexing to manage transmissions on a single wire, ensuring that headers and payloads are sent in the correct sequence with proper timing. This periodic control mechanism provides reliability through synchronized transmission while keeping the physical infrastructure simple.
Data Source
AI summary
A Network on Chip (NoC) includes a serializer connected to a transport link/channel. The serializer is configured to receive a flit composed of a header and a payload in parallel, forward the header to the transport link/channel, and forward the payload to the transport link/channel after the header has been sent/forwarded. The NoC also includes a deserializer connected to the transport link/channel of the NoC. The deserializer is configured to receive the header and the payload in a serialized manner from the transport link/channel, and send copies of the header and pass the payload in parallel to a physical output channel.