NoC Link Size Prediction via Supervised Learning
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Solution Overview
Problem
Existing Network-on-Chip (NoC) synthesis methods fail to effectively account for specific placement, routing, and traffic flow styles, leading to poorly selected link sizes that impact wiring cost, performance, and latency.
Innovation Solution
A supervised learning-based model is used to determine link sizes for each router in the NoC by generating route feature vectors and label vectors, trained on reference configurations to predict optimal link sizes, with resizers and pipeline components added as needed to optimize the network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If generic methods are used to select NoC link sizes, then the synthesis process is simple, but the wiring cost and performance are degraded
Solution Approach 1:
The patent applies parameter changes by using a machine learning model to predict optimal link size values based on input features such as traffic patterns, placement, and routing characteristics. The model outputs predicted link sizes that differ from generic fixed values, enabling optimization of wiring cost and performance while maintaining a relatively simple synthesis process.
2Loss of time
If link sizes are optimized for specific traffic patterns, then performance and latency are improved, but the synthesis complexity increases
Solution Approach 1:
The patent replaces complex manual optimization processes with a machine learning model that automatically predicts optimal link sizes. The model takes input features (traffic patterns, placement, routing) and directly outputs optimized link size values, substituting what would otherwise be a complex iterative optimization process with a more straightforward prediction-based approach.
Solution Approach 2:
The patent applies preliminary action by pre-training the machine learning model on reference NoC configurations before actual synthesis. The model learns optimal link size patterns from training data and can then quickly predict optimal values for new configurations without requiring complex real-time optimization, thus reducing synthesis complexity while improving latency performance.
3Productivity
If link sizes are selected without considering placement and routing, then the selection process is fast, but performance is suboptimal
Solution Approach 1:
The patent applies local quality by considering placement and routing-specific features as input to the machine learning model. The model predicts different link sizes for different routes and locations in the NoC based on local traffic patterns and routing characteristics, rather than using uniform link sizes everywhere. This enables fast prediction while achieving optimal local performance.
Data Source
AI summary
The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.