NOC Messaging Interconnect Inbox Outbox Latency Bandwidth
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Solution Overview
Problem
Current data processing technologies, such as pure MIMD and pure SIMD systems, are not optimized for applications that require both high parallelism and fast random access to shared memory, making them inefficient for certain real-world simulation programs.
Innovation Solution
A Network on Chip (NOC) architecture that integrates processor blocks, routers, memory communications controllers, and network interface controllers, with each processor block connected through low latency, high bandwidth application messaging interconnects, enabling efficient parallel processing and fast random access to shared memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pure MIMD system is used, then fast random access to shared memory is provided, but high degree of parallelism is not achieved
Solution Approach 1:
The system is segmented into multiple processing nodes (P0-P7) that can operate independently in parallel, while each node maintains its own local memory. This segmentation allows simultaneous execution of multiple instruction streams (improving parallelism) while each node can access its local memory at full speed (maintaining memory access speed). The interconnect network enables communication between segmented nodes when needed.
2Productivity
If pure SIMD system is used, then high degree of parallelism is achieved, but fast random access to main memory stores is not provided
Solution Approach 1:
The memory system is segmented into distributed local memories attached to each processing node, rather than a single centralized memory. Each node has direct access to its local memory at full speed, while the interconnect network provides access to remote memories. This resolves the contradiction by allowing SIMD-style parallel operations on local data while enabling fast random access to distributed memory resources.
Solution Approach 2:
The memory architecture transitions from a single-dimensional centralized memory model to a multi-dimensional distributed memory model. Each node operates in its own memory space locally, while the interconnect network provides access to other nodes' memory spaces. This dimensional expansion allows simultaneous local memory access (fast speed) and parallel processing across multiple nodes (high parallelism).
3Ease of operation
If traditional NOC architecture is used, then inter-IP block communications are controlled, but latency is high and bandwidth is limited
Solution Approach 1:
The messaging interconnect functionality is extracted from the general-purpose network interface controllers and embedded directly within each IP block as dedicated inbox and outbox structures. This extraction creates direct, low-latency communication paths between IP blocks without requiring full network protocol processing, while still maintaining controlled communication through the messaging interface.
Solution Approach 2:
Dedicated messaging interfaces (inboxes and outboxes) are introduced as intermediaries between IP blocks and the network. These intermediaries provide controlled communication by buffering and managing message flow, while their direct connection to IP blocks minimizes latency compared to traditional router-based communication.
4Ease of operation
If traditional NOC architecture is used, then inter-IP block communications are controlled, but bandwidth is low
Solution Approach 1:
Each IP block is equipped with dedicated messaging resources (inbox and outbox) that provide high-bandwidth direct communication paths. The local quality of each node is enhanced with sufficient buffer capacity and message handling capability, allowing high-volume data transfer without congesting the shared network infrastructure.
Data Source
AI summary
Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.