NoC Simulation via Multi-Message Transaction Sequences
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Network on Chip (NoC) performance simulators fail to accurately mimic multi-point inter-dependent message sequence generation behavior, leading to unrealistic synchronization of message flows and inadequate representation of complex SoC traffic patterns, which limits their ability to characterize NoC performance effectively.
Innovation Solution
The proposed solution involves performing multi-message transaction-based performance simulations within the NoC interconnect architecture, using transaction sequences with multiple messages across agents, where each message can have varying properties like rate, priority, and latency, and generating trace files to initiate and execute transactions, allowing for accurate simulation of full SoC behavior and NoC performance characterization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing NoC performance simulators use simple message flow generation, then the simulation is faster and easier to implement, but the simulation accuracy and ability to characterize real SoC traffic patterns deteriorates
Solution Approach 1:
The simulation system segments complex SoC traffic patterns into discrete transaction sequences, each consisting of multiple messages with specific properties. This allows accurate representation of real traffic patterns while maintaining manageable simulation complexity through structured decomposition.
Solution Approach 2:
The system pre-defines transaction sequences with specific message properties (rate, priority, latency) before execution. This preliminary configuration enables accurate simulation of real SoC behavior without requiring complex real-time modeling, resolving the contradiction between accuracy and complexity.
2Adaptability or versatility
If the simulator generates independent point-to-point messages, then the simulation is simpler and faster, but the ability to represent multi-point inter-dependent message sequences deteriorates
Solution Approach 1:
The system merges multiple independent point-to-point messages into unified transaction sequences that represent multi-point inter-dependent communication patterns. This combining approach enables accurate representation of complex SoC traffic while maintaining the simplicity of individual message generation through structured composition.
Solution Approach 2:
The transaction sequence framework provides a universal model that can represent various traffic patterns (point-to-point, multi-point, inter-dependent messages) using the same basic mechanism. This multi-functionality achieves high adaptability without proportionally increasing complexity.
3Productivity
If the simulator uses simplified message flow models, then the simulation execution is faster, but the realism and accuracy of synchronization characterization deteriorates
Solution Approach 1:
The system changes message properties (rate, priority, latency parameters) within transaction sequences to accurately represent real SoC synchronization behavior. By adjusting these parameters rather than using complex modeling, the system maintains simulation speed while improving synchronization characterization accuracy.
Data Source
AI summary
Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.