NoC Observer Processors for SoC Task Scheduling Contention

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Solution Overview

Problem

Independent task scheduling in system-on-chip (SoC) leads to resource contention among computing elements, resulting in high power consumption and lower system performance due to simultaneous memory access and idle periods.

Innovation Solution

A network-on-chip (NoC) with observer processors that monitor traffic load and generate real-time statistics, and an aggregator processor that identifies heavily contended targets and provides task scheduling feedback to initiators to adjust execution order and reduce contention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If independent task scheduling is implemented at each computing element, then scheduling flexibility and autonomy are improved, but resource contention and power consumption increase

Engineering Contradiction:

Improvescheduling autonomyVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent implements a feedback mechanism where observer processors monitor NoC traffic and provide information to an aggregator processor, which then generates scheduling feedback sent back to initiator computing elements. This closed-loop feedback system enables independent scheduling autonomy while coordinating resource usage to reduce contention and power consumption.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces observer processors and an aggregator processor as intermediary components between computing elements and the NoC. These intermediaries monitor traffic patterns, analyze contention, and provide scheduling guidance, enabling coordinated resource usage without requiring direct control over each computing element's local scheduler.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If multiple computing elements access shared memory simultaneously, then system throughput is improved, but resource contention and power consumption increase

Engineering Contradiction:

Improvesystem throughputVSAvoidresource contention

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The observer processors continuously monitor NoC traffic and provide real-time information about memory access patterns to the aggregator processor. This feedback enables the system to identify contention scenarios and adjust scheduling to balance throughput optimization with contention reduction.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs preliminary analysis of traffic patterns and generates scheduling feedback before contention occurs. By predicting potential contention based on monitored patterns and providing advance scheduling guidance, the system prevents harmful contention while maintaining high throughput.

Inventive Principle:

Principle #10Preliminary action

3Speed

If system operates at high frequency to serve all task needs, then task completion speed is improved, but power consumption increases

Engineering Contradiction:

Improvetask completion speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic scheduling adjustments based on real-time traffic monitoring. The system adapts task execution timing and frequency based on current NoC conditions, enabling high-speed operation when resources are available while reducing frequency and power consumption when contention is detected.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (task scheduling timing, execution frequency) based on monitored traffic patterns. By dynamically adjusting these parameters rather than operating at constant high frequency, the system maintains task completion speed while reducing power consumption during low-contention periods.

Inventive Principle:

Principle #35Parameter changes

4Device complexity

If independent scheduling is implemented, then system complexity is reduced, but system-wide coordination and performance optimization deteriorate

Engineering Contradiction:

Improvescheduling system complexityVSAvoidsystem performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent introduces lightweight observer and aggregator processors as intermediaries that provide system-wide coordination without complicating individual computing element schedulers. These intermediaries handle the complexity of global optimization while local schedulers maintain their simplicity and independence.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The scheduling system is segmented into independent local schedulers at each computing element and separate monitoring/coordination functions implemented by observer and aggregator processors. This segmentation allows local simplicity while enabling global optimization through the specialized coordinator components.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250106119A1SYSTEM AND METHOD TO CONTROL TASKS EXECUTION IN A SYSTEM-ON-CHIP (SoC) BY OBSERVING PACKETS IN A NETWORK-ON-CHIP (NoC)

Publication Date: 2025.03.27 ARTERIS INC

AI summary

A network-on-chip (NoC) provides packet-based communication between a plurality of initiator computing elements and a plurality of target computing elements. The NoC includes a plurality of observer processors upstream of and corresponding to the target computing elements. Each observer processor is configured to perform packet inspection and generate information in real-time about traffic load on its corresponding target computing element. An aggregator processor is configured to process the traffic load information from the observer processors to identify those target computing elements that are most heavily contended.