NoC Packet Switch with Ordering Queue to Resolve HoL Blocking
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Solution Overview
Problem
Network-on-chip (NoC) devices face bandwidth degradation due to the head-of-line (HoL) blocking phenomenon when using multi-channel interleaving memory, limiting the system's overall performance and bandwidth utilization.
Innovation Solution
A packet transmission switch with multiple buffers and ordering queues that allocate and store packets for simultaneous output to multiple terminals, avoiding the HoL blocking issue by determining buffer locations and using multiplexers to arbitrate packet output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-channel interleaving memory is used to increase bandwidth, then memory bandwidth capacity is improved, but head-of-line blocking occurs causing bandwidth degradation
Solution Approach 1:
The patent segments packets into multiple smaller packets and distributes them across different channels. Each packet is independently routed through the buffer and ordering queue system, allowing parallel transmission without HoL blocking. The buffer allocator assigns different buffer locations to different packets, enabling simultaneous output to multiple terminals.
Solution Approach 2:
The patent performs preliminary actions by pre-allocating buffer locations and pre-ordering packets in the ordering queue before transmission. The buffer allocator determines buffer locations in advance, and the ordering queue stores packets in the correct sequence, ensuring that packets are ready for immediate transmission without waiting for previous packets to clear.
2Ease of operation
If bus-based connection methods are used to connect modules, then connection simplicity is maintained, but bandwidth bottleneck occurs as chip integration increases
Solution Approach 1:
The patent introduces a switch with buffer and ordering queue as an intermediary component between memory channels and output terminals. This intermediary system manages packet routing and ordering, enabling multiple channels to operate in parallel without creating bandwidth bottlenecks. The switch architecture provides a mediator that coordinates multiple data paths while maintaining connection simplicity.
3Productivity
If packet transmission switch with multiple buffers and ordering queues is implemented, then bandwidth efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal switch architecture where the same buffer and ordering queue structure handles multiple channels and packet types. The buffer allocator serves all input terminals uniformly, and the ordering queue manages packets for all output terminals using the same mechanism. This multi-functional approach achieves high bandwidth efficiency while controlling complexity through standardized components.
Data Source
AI summary
A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.