Network-on-Chip Power Clock Domain Assignment

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Solution Overview

Problem

In integrated circuit design, particularly for network on chip (NoC) devices, the existing methods for assigning power and clock domains lead to increased logic area, power consumption, and latency due to the need for power and/or clock domain conversion circuits between nodes in different domains.

Innovation Solution

A computer-implemented method that detects communication paths between data handling nodes and assigns power and clock domains to data routing nodes based on the detected power domains and data traffic parameters of other nodes, optimizing the allocation to minimize the number of power and clock domain conversions required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If power and clock domain conversion circuits are added to handle data communication between nodes in different domains, then data communication capability is improved, but logic area increases

Engineering Contradiction:
Improvedata communication capabilityVSAvoidlogic area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies preliminary action by detecting communication paths and assigning power/clock domains to routing nodes before actual data transmission occurs. The system analyzes the network topology and traffic parameters in advance, pre-assigning domains to minimize the need for domain conversion circuits during operation, thereby reducing logic area while maintaining communication capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter assignment strategy by dynamically assigning power domains and clock domains to routing nodes based on detected traffic patterns and communication paths. Instead of fixed domain assignments, the system adjusts domain parameters optimally to reduce the number of domain conversion circuits required, thus reducing logic area while preserving adaptability.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If power and clock domain conversion circuits are added to handle data communication between nodes in different domains, then data communication capability is improved, but power consumption increases

Engineering Contradiction:
Improvedata communication capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The system performs preliminary detection of communication paths and pre-assignment of power/clock domains before data transmission. This advance planning minimizes the number of domain conversion circuits that need to be activated during operation, thereby reducing overall power consumption while maintaining the ability to handle communications across different domains.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent optimizes power consumption by dynamically changing the assignment of power domains and clock domains to routing nodes based on actual traffic parameters and communication paths. This parameter optimization reduces the activation of power-consuming domain conversion circuits while preserving cross-domain communication capability.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If power and clock domain conversion circuits are added to handle data communication between nodes in different domains, then data communication capability is improved, but latency increases

Engineering Contradiction:
Improvedata communication capabilityVSAvoidlatency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by detecting communication paths and optimally assigning power/clock domains to routing nodes before data transmission begins. This pre-optimization minimizes the number of domain conversion operations required during actual data flow, thereby reducing cumulative latency while maintaining the ability to communicate across different domains.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system reduces latency by dynamically changing the domain assignment parameters based on detected traffic patterns and communication paths. This optimization minimizes the number of domain conversion steps in the data path, reducing the time loss associated with domain conversions while preserving cross-domain communication capability.

Inventive Principle:
Principle #35Parameter changes

4Ease of manufacture

If existing methods assign power and clock domains without optimization, then implementation is simple, but the number of power and clock domain conversions increases

Engineering Contradiction:
Improveimplementation simplicityVSAvoidnumber of power and clock domain conversions
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by implementing a detection and assignment phase before actual domain conversion operations. The system detects communication paths and assigns domains in advance using automated algorithms, which reduces the number of conversions needed during operation. This preliminary optimization step, while adding some design complexity, significantly reduces the operational complexity of domain conversions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses parameter changes by optimizing the assignment of power domains and clock domains based on detected traffic parameters and communication paths. This systematic parameter optimization reduces the number of domain conversions required, transforming a complex operational problem into a manageable design-time assignment problem.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10318243B2Integrated circuit design
Publication Date: 2019.06.11 ARM LTD
  • US10318243B2 patent drawing
  • US10318243B2 patent drawing
  • US10318243B2 patent drawing

AI summary

A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domains and the detected data traffic parameters of the set of one or more other data handling nodes; and (iii) assigning a clock domain to said each given data routing node, from a set of one or more candidate clock domains applicable to the assigned power domain, so that said each given data routing node, operating in the assigned clock domain, provides data routing according to the detected data traffic parameters of at least those of the set of one or more other data handling nodes operating according to the assigned power domain of said each given data routing node.