Network-on-Chip Router Lifetime Arbitration for Latency Variation
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Solution Overview
Problem
Existing network-on-chip technologies face challenges in reducing variation in latency and throughput of packet transfers within the chip while minimizing the area occupied by routers, as they often require complex hardware that increases router size and can lead to biased arbitration across multiple routers.
Innovation Solution
The semiconductor chip employs routers with input/output controllers that add a predetermined value to the lifetime of deferred transfer data, prioritizing packets with the largest lifetime for transmission, thereby reducing latency variation and improving throughput with a smaller hardware footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex hardware is used to reduce latency variation and improve throughput, then data transfer performance is improved, but router area increases
Solution Approach 1:
The patent changes the parameter used for arbitration from simple round-robin counting to lifetime values embedded in packets. By using lifetime as the arbitration parameter, the system achieves better latency variation reduction without requiring complex hardware structures, thus improving productivity while controlling router area.
Solution Approach 2:
The patent replaces complex mechanical arbitration hardware with a simpler system that reads lifetime values from packets and performs comparison. This substitution of complex mechanical arbitration with a lighter-weight comparison-based system reduces router area while maintaining or improving throughput performance.
2Stability of the object's composition
If complex arbitration mechanisms are implemented to reduce latency variation, then latency uniformity is improved, but device complexity increases
Solution Approach 1:
The patent changes the arbitration criterion from complex multi-parameter considerations to a single lifetime parameter comparison. This parameter simplification reduces device complexity while effectively reducing latency variation, as the arbitration logic only needs to compare lifetime values rather than manage complex states.
Solution Approach 2:
The patent extracts the latency control function from complex arbitration mechanisms by using lifetime values that are预先 embedded in packets. This extraction allows the arbitration logic to be simpler while still achieving latency variation reduction, as the timing information is already available in the packet data.
3Device complexity
If round-robin scheduling is used for arbitration, then implementation simplicity is maintained, but latency variation increases
Solution Approach 1:
The patent changes the arbitration parameter from round-robin counter values to packet lifetime values. This parameter change maintains relative implementation simplicity while dramatically improving latency variation, as the lifetime-based arbitration naturally prioritizes packets that have been waiting longer without requiring complex state management.
Data Source
AI summary
A semiconductor chip includes modules configured to transmit transfer data, the transfer data including a lifetime corresponding to a time required to transfer the transfer data, routers including a plurality of input/output controller configured to receive and transmit the transfer data, the routers being configured to add a predetermined value to the lifetimes included in deferred transfer data, transmission of the deferred transfer data being deferred as a result of arbitration for transmitting the transfer data having a largest lifetime among a plurality of the transfer data competing for one of the input/output controller. and channels configured to connect one of the modules to one of the routers, or to connect one of the routers to an adjacent router.