Zero-Cycle Network-on-Chip Router with Parallel Arbitration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-processor system-on-chip (MPSoC) integrated circuits, the communication infrastructure often becomes a bottleneck, leading to performance issues due to latency and packet loss, especially when routing complex data packets across multiple routers.
Innovation Solution
A network-on-chip router with virtual network support is implemented, featuring multiple virtual networks, decoders for header processing, and arbitration circuitry that allocates virtual network outputs and output links in parallel, allowing for zero-cycle data transfer without packet loss by bypassing buffers when no contention exists.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional communication infrastructure is used in MPSoC, then system integration is achieved, but communication latency and packet loss occur making it a bottleneck for system performance
Solution Approach 1:
The patent segments the communication infrastructure into multiple virtual networks (VN0, VN1, VN2, VN3) that operate independently over shared physical links. This segmentation allows different data flows to be handled in parallel without interfering with each other, reducing communication latency and eliminating the bottleneck effect of traditional single-network architectures.
Solution Approach 2:
The patent introduces a virtual network dimension overlaying the physical network infrastructure. By adding this logical layer with multiple virtual networks identified by VN_IDs, the system achieves multi-dimensional data routing capabilities, enabling simultaneous data transfers that would otherwise conflict in a single-network system, thus improving productivity without increasing physical complexity.
2Productivity
If traditional arbitration is used for output link allocation, then resource sharing is achieved, but sequential processing causes latency
Solution Approach 1:
The patent implements preliminary action by performing output link arbitration in advance of virtual network output arbitration. The output link arbiter determines link allocation before the virtual network arbiter assigns virtual network outputs, allowing the system to prepare resource allocation ahead of time. This preliminary arbitration reduces latency by having arbitration results ready before data units need to be transferred.
Solution Approach 2:
The patent implements dynamic parallel arbitration where the system adapts its arbitration process based on contention conditions. When multiple data units contend for the same output link, the arbiter dynamically selects among them using round-robin or priority-based methods. This dynamic behavior allows the system to handle varying traffic patterns efficiently, maintaining high productivity under different load conditions.
3Reliability
If buffers are always used for data routing, then packet loss is prevented, but buffering introduces latency
Solution Approach 1:
The patent applies partial buffering by using bypassable buffers that are only activated when contention occurs. The bypassable input buffer and bypassable output buffer provide buffering capability when needed (when multiple data units contend for the same resource) but can be bypassed when no contention exists. This partial application of buffering maintains reliability by preventing packet loss during contention while minimizing latency during non-contention periods.
Solution Approach 2:
The patent uses temporary buffering resources that are only activated when needed. The bypassable buffers act as short-living objects that provide buffering service temporarily during contention events and then become inactive. This approach provides reliability only when necessary (when packet loss would occur) while avoiding the continuous latency penalty of always-active buffers, effectively using buffering as a disposable resource.
Data Source
AI summary
A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.