NoC Routing and DPE Compilation for Heterogeneous IC Design Flow

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Traditional design flows for heterogeneous and programmable integrated circuits (ICs) face challenges in converging hardware and software design processes, leading to inefficiencies in implementing applications due to decoupled hardware and software design, which results in suboptimal implementation of applications within ICs.

Innovation Solution

A method that generates a logical architecture and interface solutions for mapping software portions to hardware resources in programmable logic, using a processor to build block diagrams and compile software portions for implementation in data processing engines, with compilers interacting to converge on design metrics such as timing, area, and power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If hardware and software design processes are decoupled, then hardware designers can create monolithic hardware design independently, but there is no indication of software requirements or placement of interfaces between subsystems, causing design processes to fail to converge

Engineering Contradiction:

Improveindependence of hardware designVSAvoidsoftware requirements and interface placement information

Core Design Contradiction:

Ease of manufactureVSLoss of information

Solution Approach 1:

The patent merges hardware and software design processes into a unified flow where both are specified simultaneously at the architectural level. The hardware compiler and DPE compiler work together in an iterative process, sharing interface block solutions and constraints, ensuring that software requirements and interface placements are determined together rather than separately.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback loops between the hardware compiler and DPE compiler. The hardware compiler provides interface block solutions to the DPE compiler, which then generates constraints that feed back to the hardware compiler. This iterative feedback process ensures convergence on optimal interface placements and resource mappings.

Inventive Principle:

Principle #23Feedback

2Device complexity

If traditional monolithic hardware design approach is used, then hardware design is simplified, but software design becomes limiting and implementation quality is suboptimal

Engineering Contradiction:

Improvehardware design simplicityVSAvoidimplementation quality and runtime efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent segments the application into hardware portion and software portion that can be implemented in different subsystems (programmable logic and DPE array). This segmentation allows each portion to be optimized for its target substrate while maintaining a unified design process that ensures optimal interface integration and overall implementation quality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic iteration between hardware and software compilation processes. The design flow is not static but dynamically adjusts through multiple passes where compilers exchange interface solutions and constraints, allowing the system to converge on optimal implementations that balance hardware simplicity with software efficiency.

Inventive Principle:

Principle #15Dynamics

3Loss of time

If interface block solutions are not optimized, then design convergence is difficult, but runtime performance and resource utilization are suboptimal

Engineering Contradiction:

Improvedesign convergence timeVSAvoidruntime performance and resource utilization

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The patent performs preliminary actions by generating initial interface block solutions early in the design process. The hardware compiler generates interface block solutions that are then used by the DPE compiler to guide software compilation. This preliminary establishment of interface mappings accelerates design convergence while maintaining optimization potential.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces manual interface design and optimization with automated compiler-based systems. The hardware compiler and DPE compiler automatically generate and refine interface block solutions through iterative processing, substituting manual mechanical design processes with automated algorithmic optimization that achieves both convergence speed and runtime performance.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11645053B2Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices

Publication Date: 2023.05.09 XILINX INC

AI summary

Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.