Network-on-Chip Slot Table Allocation for SoC Bandwidth Bottlenecks
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Solution Overview
Problem
In complex System-on-Chip (SoC) designs, conventional bus-based communication systems become impractical due to high bus load and communication bottlenecks, necessitating a more efficient interconnect solution that can provide timing guarantees and scalable resource allocation.
Innovation Solution
Introducing a network-on-chip (NoC) architecture with hierarchical slot tables and time slot allocating units within network interfaces, allowing for efficient allocation of bandwidth and reducing bandwidth waste by nesting slot tables to accommodate varying bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a bus-based communication system is used in conventional processing systems, then the communication structure is simple, but the bus load becomes too high and communication bottleneck occurs as the number of modules increases
Solution Approach 1:
The patent segments the communication system from a single shared bus into multiple parallel communication channels. Each channel can independently transmit data between processing modules, dividing the communication load across multiple paths rather than concentrating it on a single bus, thereby reducing bus load and eliminating the communication bottleneck.
Solution Approach 2:
The patent introduces a new dimension to communication by adding multiple parallel channels instead of relying on a single sequential bus. This dimensional expansion allows simultaneous communication across different channels, transforming the communication architecture from one-dimensional (single bus) to multi-dimensional (multiple parallel channels), thereby improving overall communication efficiency.
2Adaptability or versatility
If the number of processing modules increases to implement new features, then the system functionality improves, but the bus load increases and communication bottleneck worsens
Solution Approach 1:
The patent segments communication responsibilities across multiple parallel channels, allowing each processing module to utilize different channels for different communication tasks. This segmentation enables the system to accommodate more modules without proportionally increasing the load on any single communication path, maintaining communication efficiency as system functionality expands.
Solution Approach 2:
The patent implements a universal communication architecture where multiple parallel channels can serve various functions and accommodate different processing modules. Each channel can be dynamically assigned to different module pairs based on communication needs, allowing the system to scale functionality while maintaining efficient communication through the multi-channel infrastructure.
3Adaptability or versatility
If fixed-width signal groups are used for data sequentialization, then the interface compatibility is improved, but the bandwidth allocation flexibility is reduced causing bandwidth waste
Solution Approach 1:
The patent segments the fixed-width signal group into multiple parallel channels, each capable of carrying sequentialized data. This segmentation allows the system to maintain interface compatibility through standardized signal groups while distributing the data transmission across multiple channels, thereby reducing bandwidth waste by utilizing only the necessary capacity in each channel rather than requiring all channels to operate at full width.
Solution Approach 2:
The patent introduces dynamic bandwidth allocation where the number of active channels and their utilization can be adjusted based on actual communication demands. This dynamic approach allows the system to maintain interface compatibility through standardized signal groups while flexibly allocating bandwidth resources, reducing waste by activating only the necessary channels and adjusting their usage patterns according to real-time needs.
Data Source
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AI summary
An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IPl - IP5) to enable a communication between the processing modules (IPl - IP5). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IPl - IP5). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (TO - T4) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (TO - T4) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (TO - T4).