NoC Socket Protocol Direct Indexing Logic Area

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Solution Overview

Problem

Conventional network-on-chip (NoC) interconnects require extensive logic silicon area and longer timing paths due to complex context array lookups for transaction responses, leading to slower performance.

Innovation Solution

A transaction interface protocol with a transaction ID signal in both request and response channels is used to directly identify context array entries, simplifying the interconnect topology and reducing logic complexity, enabling faster and more efficient data transfer between NoCs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional target NIUs perform context array lookup to identify oldest entry matching response packet sequence ID, then transaction response matching is achieved, but logic silicon area increases and timing paths become longer

Engineering Contradiction:
Improvetransaction response matchingVSAvoidlogic silicon area
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the complex chained list lookup logic from the target NIU and replaces it with a simplified direct indexing mechanism. The sequence ID field is used directly as an index into the context array, eliminating the need for complex search logic and reducing silicon area while maintaining matching reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter usage of the sequence ID field from being part of a complex matching algorithm to being a direct index parameter. This parameter transformation enables O(1) direct access to context array entries instead of requiring iterative search through chained lists, reducing both area and timing complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional target NIUs perform chained list lookup for context array entries, then transaction response matching is achieved, but timing paths become deeper and slower

Engineering Contradiction:
Improvetransaction response matchingVSAvoidtiming path speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent removes the iterative chained list traversal logic and replaces it with direct array indexing. This extraction of the complex search mechanism eliminates multiple logic levels and timing delays, achieving faster response matching while maintaining accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary organization of context array entries using direct indexing based on sequence ID. By pre-organizing the data structure to allow direct access, the system eliminates the need for iterative search during runtime, significantly improving timing performance.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If complex context array lookup logic is used in target NIUs, then transaction response matching is reliable, but logic levels increase and timing paths lengthen

Engineering Contradiction:
Improvetransaction response matchingVSAvoidlookup time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the essential function of context array lookup and implements it through direct indexing rather than complex chained list traversal. This removes unnecessary logic levels and timing delays while preserving the reliability of matching responses to the correct transactions.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transforms the lookup parameter from sequence ID to context array index, enabling direct access. This parameter change reduces the lookup operation from O(n) iterative search to O(1) direct access, eliminating time loss while maintaining matching reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4123468A1Network on a chip socket protocol
Publication Date: 2023.01.25 QUALCOMM TECHNOLOGIES INC
  • EP4123468A1 patent drawingFigure 1
  • EP4123468A1 patent drawingFigure 2
  • EP4123468A1 patent drawingFigure 3

AI summary

The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.