NoC Sub-network Segmentation for Interconnect Reusability
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Solution Overview
Problem
Design and verification of silicon interconnects in System-on-Chip (SoC) products are time-consuming and often require significant reworking when adapting a generic interconnect to derivative products, due to differing physical constraints, which increases development time and costs.
Innovation Solution
A Network-on-Chip (NoC) architecture is implemented as a collection of independent sub-networks that are agnostic to the SoC source map, allowing for expansion without impacting existing interconnects and enabling re-use across derivative products, with each sub-network having an independent source map.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a generic interconnect is adapted to derivative products with different physical constraints, then the interconnect can be reused across multiple products, but significant reworking of the Source Map is required
Solution Approach 1:
The interconnect is divided into independent sub-networks, each with its own Source Map. This segmentation allows each sub-network to be independently configured and reused across different derivative products without requiring global reworking of the entire interconnect architecture.
Solution Approach 2:
The patent introduces a hierarchical dimension to the Source Map organization, where Source Maps are structured in levels (e.g., L1, L2, L3) corresponding to different levels of the interconnect hierarchy. This dimensional organization enables efficient adaptation to different physical constraints by modifying only the relevant level's Source Map.
2Adaptability or versatility
If the interconnect architecture is modified to accommodate different physical constraints, then the interconnect can be customized for specific derivatives, but the development cycle is extended
Solution Approach 1:
The interconnect architecture is pre-configured with a hierarchical structure and multiple levels of Source Maps during the platform development phase. This preliminary action enables rapid customization for derivative products by simply populating or modifying the Source Maps without requiring architectural changes, thus maintaining high development efficiency.
Solution Approach 2:
The hierarchical interconnect architecture is designed to be universal and support multiple derivative products with different physical constraints. The same core interconnect structure can serve multiple functions across different products by configuring the Source Maps appropriately, eliminating the need for separate customizations.
3Adaptability or versatility
If a hierarchical interconnect structure is implemented with independent sub-networks, then the system becomes more flexible and reusable, but the overall system complexity increases
Solution Approach 1:
The interconnect is segmented into independent sub-networks that can be independently designed, verified, and reused. This segmentation reduces the complexity of the overall system by breaking down the monolithic interconnect into manageable modules with well-defined interfaces.
Solution Approach 2:
Multiple independent sub-networks are merged at the platform level to form the complete interconnect architecture. This merging approach allows the system to benefit from both the simplicity of individual sub-networks and the flexibility of the combined hierarchical structure.
Data Source
AI summary
A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.