NoC Switch Interconnect with Hierarchical Routing Tables

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Solution Overview

Problem

Existing network on chip (NOC) systems face challenges with large routing tables that occupy significant area and cause delays, especially in multi-chip applications where thousands of destinations require extensive routing table entries, leading to increased power consumption and complexity.

Innovation Solution

The implementation of hierarchical routing tables in NOC switches, which use chip, region, and interface identifiers to select output ports based on destination addresses, reducing the size and power requirements of routing tables and improving packet routing efficiency across multiple semiconductor dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional routing tables are used to route packets to thousands of destinations in multi-chip systems, then routing completeness is improved, but area occupancy and power consumption increase significantly

Engineering Contradiction:

Improverouting completenessVSAvoidrouting table area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent divides the traditional single routing table into multiple smaller routing tables organized in a tree structure with hierarchical levels. Each routing table in the hierarchy manages a subset of destinations, breaking down the large routing table problem into manageable segments that collectively provide complete routing coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the routing table structure, organizing routing information across multiple levels rather than in a single flat table. This dimensional transformation allows the system to achieve complete routing coverage while keeping individual routing tables compact.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If traditional routing tables are used to route packets to thousands of destinations, then routing completeness is improved, but power consumption increases

Engineering Contradiction:

Improverouting completenessVSAvoidrouting table power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

By segmenting the routing functionality across multiple hierarchical levels, each routing table processes only a portion of the total routing decisions. This segmentation reduces the computational burden and power consumption at each individual routing table while maintaining complete routing capability through the hierarchy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each routing table in the hierarchy performs partial routing action for its designated subset of destinations rather than processing all routing decisions. This partial action approach reduces power consumption at each stage while the cumulative effect of all routing tables provides complete routing coverage.

Inventive Principle:

Principle #16Partial or excessive action

3Adaptability or versatility

If large routing tables are implemented to support thousands of destinations, then routing capability is improved, but packet routing delay increases

Engineering Contradiction:

Improverouting capabilityVSAvoidpacket routing delay

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The hierarchical segmentation of routing tables enables parallel processing of routing decisions at different levels. Instead of searching through a single large routing table sequentially, the packet routing process is divided into multiple smaller lookup operations that can be executed more quickly at each hierarchical level.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The hierarchical routing table structure performs preliminary routing decisions at upper levels before packets reach lower levels. This preliminary action filters and directs packets early in the routing process, reducing the overall routing path length and delay compared to searching through a complete flat routing table.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10243882B1Network on chip switch interconnect

Publication Date: 2019.03.26 XILINX INC

AI summary

A disclosed network on chip includes a semiconductor die and switches disposed on the semiconductor die. Each switch has ports configured to receive packets from and transmit packets to at least two other switches. Each switch includes first circuitry that specifies a first mapping of interface identifiers of interfaces on the semiconductor die to port identifiers, and second circuitry that specifies a second mapping of region identifiers of regions of the semiconductor die to port identifiers. Each switch further includes third circuitry coupled to the first and second circuitry. The third circuitry is configured to select, in response to an input packet that specifies a destination region and a destination interface, a port based on the specification of the destination region, specification of the destination interface, first mapping, and second mapping, and output the packet on the selected port.