Network-on-Chip Synthesis Using Deadlock-Free Segmented Routing
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Solution Overview
Problem
The existing methods for designing and synthesizing networks-on-chip (NoCs) face challenges such as deadlocks, inefficient bandwidth utilization, and the difficulty in reconfiguring existing topologies to accommodate new connections without overwriting previous results.
Innovation Solution
A system and method for generating a deadlock-free NoC that uses a set of constraints and inputs to produce a NoC with all its elements placed on a chip floorplan, incorporating incremental design and synthesis of new connections while avoiding deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual design and synthesis of NoC is performed to meet performance requirements, then the NoC can be optimized for specific constraints, but the design process becomes time-consuming and complex
Solution Approach 1:
The system enables automatic self-service design where the NoC generator autonomously creates network topologies based on input constraints without requiring manual intervention. The automated synthesis process handles routing, switching, and configuration tasks that would otherwise require extensive manual design work, thereby reducing design time while maintaining optimization for given constraints.
Solution Approach 2:
The system automatically adjusts multiple parameters including data width, clock frequency, and topology configuration based on performance requirements and constraints. By dynamically changing these parameters during the synthesis process, the system optimizes the NoC design for specific constraints while eliminating the need for manual parameter tuning and iterative redesign.
2Loss of energy
If existing NoC topology is reused to accommodate new connections, then production costs are reduced, but verifying bandwidth capacity becomes challenging
Solution Approach 1:
The system incorporates automated verification that provides feedback on bandwidth capacity and topology suitability. By analyzing the existing NoC topology against new connection requirements and automatically determining if bandwidth capacity is sufficient, the system eliminates the challenge of manual verification while maintaining cost-effectiveness through topology reuse.
Solution Approach 2:
The system replaces manual verification processes with automated computational analysis. Instead of requiring designers to manually assess bandwidth capacity, the system uses algorithmic verification to automatically determine whether existing topology can accommodate new connections, thereby reducing both time and expertise requirements for verification.
3Adaptability or versatility
If NoC configuration is revised to meet changing requirements, then the design adapts to new constraints, but the process must be redone frequently causing production delays
Solution Approach 1:
The system provides dynamic reconfiguration capability where the NoC topology can be automatically adjusted to meet changing requirements. The generator can modify existing configurations or create new ones based on updated constraints, allowing the design to adapt dynamically without requiring complete redesign and thus maintaining high production speed.
Solution Approach 2:
The system performs preliminary synthesis of the NoC topology based on initial requirements, creating a foundation that can be efficiently modified for changing constraints. By preparing the basic structure in advance, the system enables rapid adaptation to new requirements without redoing the entire design process, thereby maintaining productivity while ensuring adaptability.
4Reliability
If routing paths are added to avoid deadlocks, then message transmission reliability improves, but network complexity increases
Solution Approach 1:
The system divides the routing structure into segmented paths that can be independently configured. By segmenting the routing logic and using modular switching elements, the system achieves deadlock-free operation through multiple paths while keeping individual routing components simple and manageable, thus reducing overall structural complexity.
Solution Approach 2:
The system employs universal switching elements that can perform multiple routing functions. These multi-functional switches can direct messages along different paths to avoid deadlocks while using the same hardware infrastructure, thereby improving reliability without proportionally increasing complexity since the same components serve multiple purposes.
Data Source
AI summary
System and methods are disclosed that are implemented by a tool for generation and synthesis of networks, such as a network-on-chip (NoC). The tool receives input from the user, either as a data file or through input in a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool produces the NoC with all its elements, which is a legal and meets the constraints. The tool also receives as an input performance scenarios or performance requirement that can be used to transform an existing topology to satisfy the newly added requirements. The resulting output represents the network, such as the NoC, that meets the requirements.