NoC Synthesis Tool for Constraint-Driven Floorplan Placement
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Solution Overview
Problem
The process of designing an optimal network-on-chip (NoC) for systems-on-chips is complex, time-consuming, and requires frequent redesigns due to changing requirements, leading to production delays.
Innovation Solution
A system and method that generates a NoC using a set of constraints and inputs, placing its elements on a chip floorplan, simplifying the design process by using a synthesis tool that executes a series of steps to optimize the network based on connectivity, latency, and performance requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a chip architect or designer manually creates an optimal NoC to fulfill performance requirements, then the NoC can be optimized for connectivity, latency, and throughput, but the design process becomes time-consuming and requires frequent redesigns when requirements change
Solution Approach 1:
The patent replaces the manual mechanical design process with an automated electronic design automation (EDA) tool that uses algorithms and computer-based methods to generate optimal NoC topologies. The tool accepts performance requirements as inputs and automatically produces optimized NoC designs, eliminating the need for manual iteration and redesign when requirements change.
Solution Approach 2:
The patent enables dynamic adjustment of design parameters by allowing users to modify performance requirements (connectivity, latency, throughput) and have the EDA tool automatically regenerate optimized NoC configurations. This parameter-driven approach allows rapid exploration of different design scenarios without manual redesign effort.
2Adaptability or versatility
If the NoC design is revised frequently to accommodate changing requirements, then the NoC can adapt to new constraints, but production delays occur due to the time-consuming redesign process
Solution Approach 1:
The patent creates a dynamic design system where the EDA tool can rapidly reconfigure NoC topologies in response to changing requirements. The automated nature of the tool allows the design to be flexible and adaptive without incurring the time penalties of manual redesign, enabling rapid prototyping and iteration.
Solution Approach 2:
The EDA tool performs preliminary automated optimization of the NoC design before implementation, considering multiple performance criteria simultaneously. This preliminary automated action ensures that when requirements change, the design can be quickly adjusted without requiring extensive manual rework or causing production delays.
3Ease of operation
If manual NoC design methods are used, then detailed control over the design process is possible, but the complexity of the task increases and requires significant expertise
Solution Approach 1:
The EDA tool performs self-service by automatically analyzing performance requirements, generating multiple NoC topology options, and selecting the optimal design without requiring manual intervention at each step. This reduces the complexity burden on the designer while maintaining detailed control through the automated optimization process.
Solution Approach 2:
The EDA tool acts as an intermediary between the designer's requirements and the final NoC implementation. It translates high-level performance specifications into detailed design parameters and topology configurations, reducing the complexity of direct manual design while preserving design control through the automated mediation process.
Data Source
AI summary
Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.