Network-on-Chip Synthesis for Multicore Interconnect Bottlenecks

The patent segments the interconnect architecture from a traditional bus-based monolithic structure into a Network-on-Chip (NoC) architecture with multiple independent network interfaces, switches, and communication paths. This segmentation allows each component to handle communication independently, improving overall communication performance and scalability while managing complexity through modular design.

The patent implements a universal NoC architecture that can accommodate any number of processor and memory cores through standardized network interfaces and switches. This multi-functional interconnect structure handles communication between diverse core types (processors, DSPs, memory, I/O) uniformly, enabling scalable computation capability without proportionally increasing communication complexity.

The patent replaces the mechanical/physical approach of wire scaling with an architectural approach using NoC switches and packet-based communication. Instead of relying on smaller and smaller wires to achieve higher speeds, the system uses intelligent routing, buffering, and protocol management at the switch level to maintain communication speed and efficiency without requiring aggressive wire scaling that would increase manufacturing difficulty.

The patent employs parameterized NoC architecture templates where key parameters (number of switches, buffer sizes, routing algorithms, link widths) can be customized for specific applications. This allows design exploration and optimization of power consumption and performance through parameter adjustment rather than complete redesign, significantly reducing design time while still achieving application-specific optimization.