NoC Topology Analysis for External-Dependency Deadlock Prevention
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Solution Overview
Problem
Network-on-chip (NoC) systems face potential deadlocks due to external dependencies, leading to stalled data packets and system resets, which are undesirable.
Innovation Solution
The NoC design includes a process to detect and modify the topology to resolve potential deadlocks during the design phase, using software to identify loops and reconfigure components like switches to prevent deadlock formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet-based transmission is used in NoC to improve scalability and communication efficiency, then data throughput and processing power are enhanced, but deadlock conditions may occur causing system stalls
Solution Approach 1:
The patent applies preliminary action by detecting potential deadlocks during the design phase using topology analysis algorithms. The system identifies cyclic dependencies in data flow paths before implementation, allowing preventive measures to be taken during topology modification rather than reacting to deadlocks after they occur in the running system.
Solution Approach 2:
The patent introduces an intermediary analysis tool that examines the NoC topology and identifies potential deadlock conditions. This intermediary system analyzes data flow paths, external dependencies, and routing configurations to detect cyclic dependencies without interfering with the actual packet transmission operations of the NoC.
2Adaptability or versatility
If external dependencies are introduced to enable complex data flow patterns, then communication flexibility is improved, but deadlock risk increases due to cyclic dependencies
Solution Approach 1:
The system performs preliminary topology analysis to detect external dependencies that could create cyclic data flow paths. By analyzing the topology before configuration, the system identifies potential deadlock scenarios involving external dependencies and allows designers to modify the topology or data flow patterns to eliminate these risky dependencies.
Solution Approach 2:
The patent implements feedback mechanisms where the topology analysis tool provides information about potential deadlock conditions to the designer. This feedback loop allows iterative modification of the NoC topology and data flow configurations to achieve flexible communication patterns while avoiding cyclic dependencies that would cause deadlocks.
3Reliability
If system reset is used to resolve actual deadlocks, then stuck packets can be released, but system performance deteriorates due to shutdown requirements
Solution Approach 1:
By detecting potential deadlocks during the design phase through topology analysis, the system eliminates the need for runtime deadlock resolution via system resets. The preliminary identification and prevention of deadlock conditions ensures that packets can flow through the NoC without requiring system shutdowns, maintaining continuous operation and high performance.
Data Source
AI summary
Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.