Network-on-Chip Topology Modification With Incremental Synthesis
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Solution Overview
Problem
Existing NoC topology synthesis tools require extensive rework and time when small modifications are made to SoC designs, leading to inefficiencies and high costs due to the need to redo logic synthesis and place and route processes.
Innovation Solution
A topology modification tool that takes an existing NoC topology and updated requirements to generate a modified NoC topology that meets new requirements while minimizing delays and errors, using incremental synthesis steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the synthesis tool is run again with updated requirements after removing a component, then the new requirements are fulfilled, but all previous work on logic synthesis and place and route needs to be performed again from scratch
Solution Approach 1:
The patent segments the NoC topology modification process into independent analysis and application phases. The modification analysis module analyzes the impact of changes on the NoC topology independently, while the modification application module applies changes selectively. This segmentation allows only the affected portions of the design to be re-synthesized rather than the entire design, significantly reducing the time loss when requirements change.
2Reliability
If the synthesis tool is run again with updated requirements after design changes, then the new requirements are fulfilled, but the modification process becomes difficult and error prone
Solution Approach 1:
The patent introduces a modification analysis module as an intermediary between the design changes and the synthesis tool. This intermediary automatically analyzes the impact of changes on the NoC topology, determines the minimal set of modifications required, and prepares a structured modification plan. This intermediary layer simplifies the overall modification process by systematically handling the complexity of analyzing and applying changes to the NoC topology.
3Reliability
If the synthesis tool is run again with updated requirements, then the new requirements are fulfilled, but extensive rework is required leading to high costs
Solution Approach 1:
The patent performs preliminary analysis of the impact of design changes on the NoC topology before actually running the full synthesis process. The modification analysis module pre-evaluates which components and connections are affected by the changes, allowing the system to prepare a targeted modification plan in advance. This preliminary action enables selective re-synthesis of only the affected portions, reducing extensive rework and lowering the cost of design modifications.
Data Source
AI summary
An existing network-on-chip (NoC) topology that is derived based on a set of initial requirements is changed using incremental modifications that satisfy a set of updated requirements. Each incremental modification includes minimizing the number of changes to existing components in the existing NoC topology. Minimizing the changes includes preserving names of the existing components in the existing NoC topology and removing existing components or connections as well as adding in new component and new connections.